Abstract
This paper is dealing with the reconfiguration of a flexible real-time Network-on-Chip (NoC) in Multiprocessors System-on-Chip MPSoC architectures. We assume that each NoC’s node is composed of a processor and a router. A processor is assumed to be composed of dependent periodic and aperiodic operating system tasks. The paper addresses low-power adaptations of MPSoC when dynamic reconfigurations of the periodic and aperiodic tasks (sharing resources) are applied at run-time to save or improve the performance. The reconfiguration is defined as any operation allowing the addition-removal-update of periodic dependent OS (Operating System) tasks that share resources. For two added dependent tasks assigned to different processors, a message is added automatically on the NoC. After a such scenario, several real-time constraints may be violated and the power consumption increased.In order to resolve this problem, a new approach CRMPSoC (Abbrev. Cynapsys-Reconfigurable MPSoC) that is composed of two steps is proposed: (1) Applying a reconfiguration: Selection of reconfiguration scenarios, and (2) System Feasibility: A multi-agent architecture based on a master/slave model is defined where a slave agent is assigned to each node to verify the system/bus feasibility, and a master is proposed for the whole architecture if any perturbation occurs at run-time by proposing software or hardware solutions. Since the kernel is not reconfigurable, we develop a new middleware that will support the different steps of our approach. The latter is applied to a real case study for the evaluation of the paper’s contribution.
This research work is carried out within a MOBIDOC PhD thesis of the PASRI program, EU-funded and administered by ANPR (Tunisia). This national project is a collaboration between LISI Lab at University of Carthage, Cynapsys (French-German company installed in Tunisia), Systems Control Lab at Xidian University in China and Macau University of Science and Technology in Macau. We thank all directors of Cynapsys for their technical and financial stable supports. Special thank to all Master and Graduate Students who partially supported this project. This work is partially supported by Science and Technology Development Fund, MSAR, under Grant No. 066/2013/A2.
M. Khalgui is also with ITIA Institute, National Council of Research, Rome 00161, Italy.
Z.W. Li is also with the Faculty of Engineering, King Abdulaziz University, Jeddah 21589, Saudi Arabia.
Change history
02 February 2019
The original version of the chapter “CRMPSoC: New Solution for Feasible Reconfigurable MPSoC”, starting on p.175 was revised. An affiliation has been added. The original chapter was corrected.
Notes
- 1.
We are very grateful for the company Cynapsys which provides us this FPGA. It is characterized by: (a) High-performance Stratix III EP3SL150F1152 FPGA, (b) DDR2 SDRAM and QDR II SRAM, (c) PSRAM and flash memory, (d) USB 2.0 MAC/PHY, (e) Graphics and character LCD displays, and (f) On-board embedded USB-BlasterTM download cable.
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Khemaissia, I., Mosbahi, O., Khalgui, M., Li, Z. (2017). CRMPSoC: New Solution for Feasible Reconfigurable MPSoC. In: Cabello, E., Cardoso, J., Ludwig, A., Maciaszek, L., van Sinderen, M. (eds) Software Technologies. ICSOFT 2016. Communications in Computer and Information Science, vol 743. Springer, Cham. https://doi.org/10.1007/978-3-319-62569-0_9
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