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Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study

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Constructive Side-Channel Analysis and Secure Design (COSADE 2017)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 10348))

Abstract

Dual-rail logic styles have been considered as possible alternatives to CMOS for the design of cryptographic circuits (more) secure against side-channel attacks. The state-of-the-art view on this approach is contrasted as they reduce the exploitable side-channel signal while not being sufficient to fully prevent the attacks. Since the limitations of dual-rail logic styles are essentially due to implementation challenges (e.g. the need of well-balanced capacitances), a natural question is to find out how they evolve with technology scaling. In this paper, we discuss this issue based on the relevant case study of an AES S-box implemented in CMOS and a dual-rail logic style, for two (65 nm and 28 nm) technologies. Our evaluations show that the security vs. performance tradeoff of our dual-rail logic style does not scale well compared to CMOS. It also shows that the scaling trends for CMOS are more positive (i.e. smaller technologies and supply voltages reduce the energy consumption and the side-channel signal). So these results suggest that dual-rail logic style may not be a sustainable approach for side-channel signal reduction as we move towards lower technology nodes.

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Notes

  1. 1.

    Note that advanced technologies usually provide multiple flavors such as low-power and high-performance along with different device choices such as high and low threshold voltages, providing circuit designers with various options to reduce the power consumption – and the leakage power as well – which may modify the respective importance of these source of leakages.

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Acknowledgments

This work has been funded in parts by the ARC Project NANOSEC. François-Xavier Standaert is a research associate of the Belgian Fund for Scientific Research.

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Authors and Affiliations

  1. ICTEAM/ELEN/Crypto Group, Université catholique de Louvain, Louvain-la-Neuve, Belgium

    Kashif Nawaz, Dinal Kamel, François-Xavier Standaert & Denis Flandre

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  1. Kashif Nawaz
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Correspondence to Kashif Nawaz .

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  1. Secure-IC S.A.S. and TELECOM-ParisTech, Paris, France

    Sylvain Guilley

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Nawaz, K., Kamel, D., Standaert, FX., Flandre, D. (2017). Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study. In: Guilley, S. (eds) Constructive Side-Channel Analysis and Secure Design. COSADE 2017. Lecture Notes in Computer Science(), vol 10348. Springer, Cham. https://doi.org/10.1007/978-3-319-64647-3_2

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  • DOI: https://doi.org/10.1007/978-3-319-64647-3_2

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