Abstract
Side-channel analysis attacks, particularly power analysis attacks, have become one of the major threats, that hardware designers have to deal with. To defeat them, the majority of the known concepts are based on either masking, hiding, or rekeying (or a combination of them). This work deals with a hiding scheme, more precisely a power-equalization technique which is ideally supposed to make the amount of power consumption of the device independent of its processed data. We propose and practically evaluate a novel construction dedicated to Xilinx FPGAs, which rules out the state of the art with respect to the achieved security level and the resource overhead.
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Notes
- 1.
The exact number of available resources in an FPGA highly depends on its device family and differs between the available architectures and manufacturer.
- 2.
This failure appears on the Kintex-7 if the FF and the LUT controlled by the same active signal are placed at the same slice.
- 3.
Since we reuse the active signals to control stages of all circuit parts, we should consider the highest stage delay at all circuit parts.
- 4.
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Ender, M., Wild, A., Moradi, A. (2017). SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA. In: Guilley, S. (eds) Constructive Side-Channel Analysis and Secure Design. COSADE 2017. Lecture Notes in Computer Science(), vol 10348. Springer, Cham. https://doi.org/10.1007/978-3-319-64647-3_6
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DOI: https://doi.org/10.1007/978-3-319-64647-3_6
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