Skip to main content

NoC-Based Thread Synchronization in a Custom Manycore System

  • Conference paper
  • First Online:
Advances on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC 2017)

Abstract

This workshop paper presents an efficient hardware support for thread synchronization in a customized manycore system developed within the MANGO H2020 project. The solution relies on a distributed master and on a lightweight control unit on the core side, using hardware-level messages and thus avoiding memory accesses. It supports multiple barriers for different application kernels executed simultaneously. The results for different NoC sizes provide indications about the reduced synchronization times and the area overheads incurred by our solution.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Paranjape, K., Hebert, S., Masson, B.: Heterogeneous computing in the cloud: crunching big data and democratizing HPC access for the life sciences. Intel Corporation, Technical report (2010)

    Google Scholar 

  2. Barbareschi, M., Mazzeo, A., Vespoli, A.: Network traffic analysis using android on a hybrid computing architecture. In: International Conference on Algorithms and Architectures for Parallel Processing, pp. 141–148. Springer (2013)

    Google Scholar 

  3. Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. ACM Comput. Surv. 38(1), 1 (2006)

    Article  Google Scholar 

  4. Cilardo, A., Fusella, E., Gallo, L., Mazzeo, A.: Automated synthesis of FPGA-based heterogeneous interconnect topologies. In: International Conference on, Field Programmable Logic and Applications (FPL) (2013)

    Google Scholar 

  5. Amato, F., Moscato, F.: Pattern-based orchestration and automatic verification of composite cloud services. Comput. Electr. Eng. 56, 842–853 (2016)

    Article  Google Scholar 

  6. Fusella, E., Cilardo, A.: Lighting up on-chip communications with photonics: design tradeoffs for optical NoC architectures. IEEE Circ. Syst. Manag. 16(3), 4–14 (2016)

    Article  Google Scholar 

  7. Hoefler, T., Mehlan, T., Mietke, F., Rehm, W.: A Survey of Barrier Algorithms for Coarse Grained Supercomputers. Chemnitzer Informatik Berichte. Technische Universität Chemnitz, Chemnitz (2004)

    Google Scholar 

  8. Fusella, E., Cilardo, A.: H2ONoC: a hybrid optical electronic NoC based on hybrid topology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(1), 330–343 (2017)

    Article  Google Scholar 

  9. Barbareschi, M., Battista, E., Mazzocca, N., Venkatesan, S.: A hardware accelerator for data classification within the sensing infrastructure. In: International Conference on Information Reuse and Integration (IRI), pp. 400–405. IEEE (2014)

    Google Scholar 

  10. Amato, F., Moscato, F.: Exploiting cloud and workflow patterns for the analysis of composite cloud services. Future Gener. Comput. Syst. 67, 255–265 (2017)

    Article  Google Scholar 

  11. Wentzlaff, D., et al.: On-chip interconnect architecture of the tile processor. IEEE Micro 27(5), 15–31 (2007)

    Article  Google Scholar 

  12. Vangal, S., et al.: An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS. In: IEEE International Conference on Solid-State Circuits (ISSCC). IEEE (2007)

    Google Scholar 

  13. Olofsson, A.: Epiphany-V: a 1024 processor 64-bit RISC system-on-chip. arXiv preprint arXiv:1610.01832 (2016)

  14. Cilardo, A., Fusella, E., Gallo, L., Mazzeo, A.: Joint communication scheduling and interconnect synthesis for FPGA-based manycore systems. In: Design, Automation and Test in Europe Conference and Exhibition (DATE) (2014)

    Google Scholar 

  15. Villa, O., Palermo, G., Silvano, C.: Efficiency and scalability of barrier synchronization on NoC based manycore architectures. In: Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp. 81–90 (2008)

    Google Scholar 

  16. Cilardo, A., Fusella, E., Gallo, L., Mazzeo, A.: Exploiting concurrency for the automated synthesis of MPSoC interconnects. ACM Trans. Embed. Comput. Syst. (TECS) 14(3), 57 (2015)

    Google Scholar 

  17. Zhu, W., et al.: Synchronization state buffer: supporting efficient fine-grain synchronization on manycore architectures. ACM SIGARCH Comput. Archit. News 35(2), 35–45 (2007)

    Article  Google Scholar 

  18. Tseng, Y.-L., Huang, K.-H., Lai, B.-C.C.: Scalable mutli-layer barrier synchronization on NoC. In: International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE (2016)

    Google Scholar 

  19. Culler, D., Singh, J.P., Gupta, A.: Parallel Computer Architecture, A Hardware/Software Approch. Morgan Kaufmann, San Francisco (1998)

    Google Scholar 

  20. Cilardo, A., Fusella, E.: Design automation for application-specific on-chip interconnects: a survey. Integr. VLSI J. 52, 102–121 (2016)

    Article  Google Scholar 

  21. Abellán, J.L., Fernández, J., Acacio, M.E.: Efficient hardware barrier synchronization in manycore CMPs. IEEE Trans. Parallel Distrib. Syst. 23(8), 1453–1466 (2012)

    Article  Google Scholar 

  22. Monchiero, M., Palermo, G., Silvano, C., Villa, O.: Efficient synchronization for embedded on-chip multiprocessors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(10), 1049–1062 (2006)

    Article  Google Scholar 

Download references

Acknowledgments

This work is supported by the European Commission in the framework of the H2020-FETHPC-2014 project n. 671668 - MANGO: exploring Manycore Architectures for Next-Generation HPC systems.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Alessandro Cilardo .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer International Publishing AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Cilardo, A., Gagliardi, M., Passaretti, D. (2018). NoC-Based Thread Synchronization in a Custom Manycore System. In: Xhafa, F., Caballé, S., Barolli, L. (eds) Advances on P2P, Parallel, Grid, Cloud and Internet Computing. 3PGCIC 2017. Lecture Notes on Data Engineering and Communications Technologies, vol 13. Springer, Cham. https://doi.org/10.1007/978-3-319-69835-9_63

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-69835-9_63

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-69834-2

  • Online ISBN: 978-3-319-69835-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics