Abstract
Prime number generation and the large number operations directly affect the efficiency of RSA encryption algorithm. In order to reduce the number of the calculation process about modular operation and to reduce the difficulty of division in the calculation process, the Montgomery optimization algorithm is used to carry out the modular multiplication of RSA encryption algorithm, so that the efficiency of the algorithm is improved. Based on the application and research of hardware implementation to information encryption, the Verilog hardware description language is used to design the RSA encryption algorithm in 1024 bits. The simulation results of encryption and decryption experiment show that Montgomery modular multiplication algorithm and RSA encryption algorithm are verified to be correct and effective.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Adleman, L., Rivest, R.: The use of public key cryptography in communication system design. Commun. Soc. Mag. 16, 20–23 (1978)
Yan, G.X.: Information security under encryption technology. Netw. Secur. Technol. Appl. 393, 100–104 (2013). (in Chinese)
Hentabli, W., Merazka, F.: An extension of RSA_512 to RSA_1024 core under hardware platform based on Montgomery powering. In: International Conference for Internet Technology and Secured Transactions, pp. 448–453 (2013)
Tamura, S., Yamada, C., Ichikawa, S.: Implementation and evaluation of modular multiplication based on coarsely integrated operand scanning. In: Networking and Computing, pp. 334–335 (2012)
Tenca, A.F., Ruggiero, W.V.: CRT RSA decryption: modular exponentiation based solely on Montgomery multiplication. In: Asilomar Conference on Signals, Systems and Computers, pp. 431–436 (2015)
Liu, Z., Jing, J., Xia, L.: An optimized architecture to speed up the Montgomery modular. In: International Conference on Computers, Communications, Control and Automation, pp. 58–62 (2011)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Cao, B., Xu, T., Wu, P. (2018). RSA Encryption Algorithm Design and Verification Based on Verilog HDL. In: Gu, X., Liu, G., Li, B. (eds) Machine Learning and Intelligent Communications. MLICOM 2017. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 226. Springer, Cham. https://doi.org/10.1007/978-3-319-73564-1_55
Download citation
DOI: https://doi.org/10.1007/978-3-319-73564-1_55
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-73563-4
Online ISBN: 978-3-319-73564-1
eBook Packages: Computer ScienceComputer Science (R0)