Abstract
Hybrid main memory including DRAM and non-volatile memory (NVM) such as phase change memory (PCM) has became a perfect substitute to DRAM-based main memory. Because it has the advantage about high performance and energy-efficient in embedded systems. The effective management of last level cache is very important which can reduce cache misses and has important practical significance on the improvement of overall system performance. In last level caches, the common used cache replacement algorithm Least Recently Used (LRU) may cause cache pollution by inserting non-reusable data into the cache. In this article we research the hybrid main memory but now the existing cache policies fail to fully solve the asymmetry between the operations of NVM and DRAM. To solve these problems we mentioned above, we propose a Process-based Pollute Region Isolation (PPRI) algorithm for improving the efficiency of last level cache utilization. It is a good way to eliminate competition between reusable and nonreusable cache lines. We also propose an improved last-level cache management scheme ILRU for the hybrid main memory which improves the cache hit ratio and minimizes write-backs to PCM. Experimental results show that the proposed framework can get better performance (average improved 17.39%) and more energy saving (average decreased 12.46%) compared with the latest cache management schemes for hybrid main memory architecture.
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This research is supported by the key Project of DEGP #2014GKCG031.
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Zheng, H., Ming, Z., Qiu, M., Zhang, X. (2018). Research on Optimizing Last Level Cache Performance for Hybrid Main Memory. In: Qiu, M. (eds) Smart Computing and Communication. SmartCom 2017. Lecture Notes in Computer Science(), vol 10699. Springer, Cham. https://doi.org/10.1007/978-3-319-73830-7_15
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DOI: https://doi.org/10.1007/978-3-319-73830-7_15
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