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Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors

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Architecture of Computing Systems – ARCS 2018 (ARCS 2018)

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Abstract

To achieve energy savings while maintaining adequate performance, system designers and programmers wish to create the best possible match between program behavior and the underlying hardware. Well-known current approaches include DVFS and task migrations in heterogeneous platforms such as big.LITTLE processors. Additionally, processors have been proposed in literature that are able to adapt (parts of) their organization to the workload. These reconfigurations can be managed using hardware monitors, profiling and other compile-time information or a combination of both. Many current solutions are suitable for heterogeneous systems, as migration penalties pose a practical limit to the maximum adaptation frequency, but not for dynamic processors that can adapt much more fine-grained.

In this paper, we present two novel concepts to aid these low-penalty reconfigurable processors - one requiring an ISA extension and one without. Our experimental results show that our approaches enable a dynamic processor to reduce the energy-delay product by up to 25% and on average 10% to 18% compared to the best performing static setups.

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Notes

  1. 1.

    On HMPs, measuring performance on one core type does not provide information about the performance on the other core type (see [9, Sect. 6.3]). To monitor which core type is the most efficient, the program needs to be migrated back and forth continuously. The same holds for different configurations of an adaptable processor.

  2. 2.

    Note that in that case, it is no longer indexed by the branch target but rather the PC of the branch itself; the buffer will return the predicted branch target and we propose to add the code information for that branch target to the entry.

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Acknowledgements

This work has been supported by the ALMARVI European Artemis project nr. 621439.

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Authors and Affiliations

  1. Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands

    Joost Hoozemans, Jeroen van Straten, Zaid Al-Ars & Stephan Wong

Authors
  1. Joost Hoozemans
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  2. Jeroen van Straten
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  3. Zaid Al-Ars
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  4. Stephan Wong
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Corresponding author

Correspondence to Joost Hoozemans .

Editor information

Editors and Affiliations

  1. Chair for Chip Design for Embedded Computing, Technische Universität Braunschweig, Braunschweig, Germany

    Mladen Berekovic

  2. Chair for Chip Design for Embedded Computing, Technische Universität Braunschweig, Braunschweig, Germany

    Rainer Buchty

  3. Institute of Computer Engineering, Universität zu Lübeck, Lübeck, Germany

    Heiko Hamann

  4. School of Computer Science, The University of Manchester, Manchester, United Kingdom

    Dirk Koch

  5. Institute for Information Technology and Communications, Otto-von-Guericke Universität Magdeburg, Magdeburg, Germany

    Thilo Pionteck

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Hoozemans, J., van Straten, J., Al-Ars, Z., Wong, S. (2018). Evaluating Auto-adaptation Methods for Fine-Grained Adaptable Processors. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_19

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  • DOI: https://doi.org/10.1007/978-3-319-77610-1_19

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