Abstract
Synchronization mechanisms have been central issues in the race toward the computing units parallelization. Indeed when the number of cores increases, the applications are split into more and more software tasks, leading to the higher use of synchronization primitives to preserve the initial application services. In this context, providing efficient synchronization mechanisms turns to be essential to leverage parallelism offered by Multi-Processor Systems-on-Chip.
By using an instrumented emulation platform allowing us to extract accurate timing information, in a non-intrusive way, we led a fine analysis of the synchronization barriers of the GNU OpenMP library. This study reveals that a time expensive function was uselessly called during the barrier awakening process. We propose here a software optimization of this library that saves up to \(80\%\) of the release phase duration for a 16-core MSoCs. Moreover, being localized into the middle-ware OpenMP library, benefiting this optimization requires no specific care from the application programmer’s point of view, but a library update and can be used on every kinds of platform.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
gem5. http://gem5.org
NAS parallel benchmarks. https://www.nas.nasa.gov/publications/npb.html
Tilera corporation. http://www.mellanox.com/repository/solutions/tile-scm/docs/UG130-ArchOverview-TILE-Gx.pdf
Abellan, J., Fernandez, J., Acacio, M.: Efficient hardware barrier synchronization in many-core CMPs. IEEE Trans. Parallel Distrib. Syst. 23(8), 1453–1466 (2012)
Buchmann, R., Greiner, A.: A fully static scheduling approach for fast cycle accurate systemC simulation of MPSoCs. In: 2007 International Conference on Microelectronics, pp. 101–104 (2007)
Hoefler, T., Mehlan, T., Mietke, F., Rehm, W.: A survey of barrier algorithms for coarse grained supercomputers. Chemnitzer Informatik Berichte 04(03) (2004). ISSN: 0947-5152. http://www.unixer.de/~htor/publications/
Leiserson, C.E., et al.: The network architecture of the connection machine CM-5. In: Proceedings of the Fourth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 1992, pp. 272–285. ACM (1992)
Monchiero, M., Palermo, G., Silvano, C., Villa, O.: Efficient synchronization for embedded on-chip multiprocessors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(10), 1049–1062 (2006)
Soga, T., Sasaki, H., Hirao, T., Kondo, M., Inoue, K.: A flexible hardware barrier mechanism for many-core processors. In: Asia and South Pacific Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, pp. 61–68 (2015)
Villa, O., Palermo, G., Silvano, C.: Efficiency and scalability of barrier synchronization on NoC based many-core architectures. In: Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2008, pp. 81–90. ACM (2008)
Wei, Z., Liu, P., Sun, R., Ying, R.: TAB barrier: hybrid barrier synchronization for NoC-based processors. In: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 409–412 (2015)
Zhengbin, P., Shaogang, W., Dan, W., Pingjing, L.: Hardware acceleration of barrier communication for large scale parallel computer. In: 2013 8th International ICST Conference on Communications and Networking in China (CHINACOM), pp. 610–614 (2013)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
France-Pillois, M., Martin, J., Rousseau, F. (2018). Optimization of the GNU OpenMP Synchronization Barrier in MPSoC. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_5
Download citation
DOI: https://doi.org/10.1007/978-3-319-77610-1_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-77609-5
Online ISBN: 978-3-319-77610-1
eBook Packages: Computer ScienceComputer Science (R0)