Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach

Abstract

Reconfigurable SRAM-based FPGAs are increasingly attractive for high performance reconfigurable computing cores due to their flexibility, upgradability and computational capabilities. In general, Partial Reconfiguration (PR) improves the reconfigurable computing paradigm due to the possibility to modify only a portion of the FPGA’s configuration memory, which results in reduced reconfiguration time. However, the speed-up gain SRAM-based FPGAs are able to achieve relies on the efficiency of the mechanism adopted to load frames in the FPGA’s configuration memory. Despite the advantages of configuration memory Partial Reconfiguration, the lack of tools and design software to implement efficient frame-oriented configuration makes PR performance less powerful then expectation. In this work, we propose an approach to reduce the reconfiguration time of routing resources exploiting a frame-driven routing algorithm able to drastically reduce the number of configuration memory frames used in the design. The advantage of the proposed solution has been applied to several benchmark circuits implemented with our routing algorithm on a Xilinx Kintex-7 SRAM-based FPGA. Experimental results shown a reduction of the used configuration frames of more than 40% on the average and a measured reconfiguration time reduced of more than 35% with respect to traditional reconfiguration approaches.