Abstract
The use of program tracing subsystems is already ubiquitous during the validation phase of an application’s life-cycle. However, these functionalities are also extremely useful in the domain of embedded fault tolerance. In this paper we explore the ARM CoreSight Debug and Trace architecture as a new tool for fault diagnosis and control flow assurance. The CoreSight is a dedicated ARM architecture that provides support for Program Flow Tracing without overhead costs for the running application. New FPGA integrated System-on-Chips (SoCs) enable the implementation of Hardware modules with direct access to system peripherals, bypassing the use of external control interfaces such as JTAG or Serial Wire Debug (SWD). We show here a new implementation for an integrated configurable hardware controller that can collect and send program trace data for a ARM Cortex-A9 integrated FPGA SoC. We also propose the use of this interface to measure hang latency, the time between the occurrence of a fault and failure detection.
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Hoppe, A.W., Kastensmidt, F.L., Becker, J. (2018). Control Flow Analysis for Embedded Multi-core Hybrid Systems. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_39
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DOI: https://doi.org/10.1007/978-3-319-78890-6_39
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