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High-Speed Finite State Machine Design by State Splitting

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Contemporary Complex Systems and Their Dependability (DepCoS-RELCOMEX 2018)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 761))

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Abstract

A synthesis method of high-speed finite state machines (FSMs) in field programmable gate arrays (FPGAs) based on LUT (Look Up Table) by internal state splitting is offered. Estimations of the number of LUT levels are presented for an implementation of FSM transition functions in the case of sequential and parallel decomposition. Split algorithms of FSM internal states for the synthesis of high-speed FSMs are described. The method can be easily included in designing the flow of digital systems in FPGA. The experimental results showed a high efficiency of the offered method. FSM performance increased by 1.73 times. In conclusion, the experimental results were considered, and prospective directions for designing high-speed FSMs are specified.

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Correspondence to Damian Borecki .

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Borecki, D., Salauyou, V., Grzes, T. (2019). High-Speed Finite State Machine Design by State Splitting. In: Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds) Contemporary Complex Systems and Their Dependability. DepCoS-RELCOMEX 2018. Advances in Intelligent Systems and Computing, vol 761. Springer, Cham. https://doi.org/10.1007/978-3-319-91446-6_7

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