Abstract
Many modern mobile processors support new SIMD extensions (e.g. NEON engine) and previous applications (e.g. image processing, cryptography) written in SISD are accelerated by re-writing the previous implementations in SIMD instruction sets. Particularly, integer multiplication and squaring operations are the most expensive in Public Key Cryptography (PKC). Many works have been conducted to reduce the execution timing in NEON instruction set. However, ARM–NEON processor also supports powerful ARM instruction set as well. By exploiting the ARM instruction together with NEON engine, we can achieve further improved performance. After this observation, we introduce new parallel approach for integer multiplication and squaring operations on ARM–NEON processors. Unlike previous implementations, we mix-use both ARM and NEON instructions to hide computation latency for ARM into NEON. Since ARM and NEON modules are separated units, the assignments are successfully issued independently. The integer multiplication and squaring are finely divided into several sub-tasks and the sub-tasks are properly assigned to ARM and NEON in order to balance the workloads. Finally, the proposed implementations outperform the best-known results on the identical ARM–NEON processors by 22.4% and 18.3% for 2048-bit integer multiplication and squaring, respectively.
This work was supported by the Energy Efficiency & Resources Core Technology Program of the Korea Institute of Energy Technology Evaluation and Planning (KETEP), granted financial resource from the Ministry of Trade, Industry & Energy, Republic of Korea. (No. 20152000000170). Hwajeong Seo was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2017-2014-0-00743) supervised by the IITP (Institute for Information & communications Technology Promotion). Zhi Hu was partially supported by the Natural Science Foundation of China (Grant No. 61602526).
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Notes
- 1.
When m-bit multiplication is required, one m-bit multiplication is evenly divided into 4 m/2-bit multiplication operations. Among them 3 m/2-bit multiplication is performed in COS method on NEON engine. On ARM processor, m/2-bit multiplication is performed in hybrid-scanning method (width: 64-bit).
- 2.
\(\mathtt{umlal\; a,b,c,d:}\; \{\mathtt{b,a}\} \leftarrow \{\mathtt{b,a}\}+ \mathtt{c} \times \mathtt{d}\).
- 3.
If we define multi-core processing through OpenMP library and execute multiple threads, the performance is enhanced by the number of threads.
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Seo, H., Park, T., Ji, J., Hu, Z., Kim, H. (2018). ARM/NEON Co-design of Multiplication/Squaring. In: Kang, B., Kim, T. (eds) Information Security Applications. WISA 2017. Lecture Notes in Computer Science(), vol 10763. Springer, Cham. https://doi.org/10.1007/978-3-319-93563-8_7
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