Skip to main content
Springer Nature Link
Log in

Embedded Classifiers for Energy-Constrained IoT Network Security

  • Chapter
Cyber-Physical Systems Security

  • 1391 Accesses

Abstract

We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Energy-constrained IoT systems, such as wearable devices, are already sensor rich and processing/computation constrained. The digital energy efficiency wall constrains the amount of signal processing possible at energy-constrained nodes. One rarely has any computational resources left to consider network security, leaving devices exposed. Fortunately many of these devices have infrequent wireless communication with very constrained command structures, but they still exhibit a system vulnerability, particularly when monitoring or controlling physical infrastructure. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. V. Asharani, B.N. Veerappa, M. Rafi, Security evaluation of pattern classifiers in adversarial environments. Int. J. Comput. Sci. Mobile Comput. 4(4), 768–774 (2015)

    Google Scholar 

  2. T. Bakhshi, B. Ghita, On internet traffic classification: a two-phased machine learning approach. J Comput. Netw. Commun. 1–21 (2016)

    Article  Google Scholar 

  3. R. Bar-Yanai, M. Langberg, D. Peleg, L. Roditty, Realtime classification for encrypted traffic, in SEA (2010), pp. 373–385

    Google Scholar 

  4. A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, C. Petre, S. Koziol, F. Baskaya, C. Twigg, P. Hasler, A floating-gate-based field-programmable analog array. IEEE J. Solid-State Circuits 45(9), 1781–1794 (2010)

    Article  Google Scholar 

  5. B. Biggio, G. Fumera, F. Roli, Security evaluation of pattern classifiers under attack. IEEE Trans. Knowl. Data Eng. 26(4), 984–996 (2014)

    Article  Google Scholar 

  6. C. Bormann, M. Ersue, A. Ericsson, Terminology for constrained-node networks, in RFC 7228. Internet Engineering Task Force (IETF) (2014)

    Google Scholar 

  7. A.A. Cardenas, J.S. Baras, Evaluation of classifiers: practical considerations for security applications (2006)

    Google Scholar 

  8. R. Chakraborty, C. Lamech D. Acharyya, J. Plusquellic, A transmission gate physical unclonable function and on-chip voltage- to-digital conversion technique, in IEEE DAC (2013), pp. 59:1–59:10

    Google Scholar 

  9. M. Collins, J. Hasler, S. George, An open-source toolset enabling analog–digital software codesign. J. Low Power Electron. Appl. 6(1), 3 (2016)

    Article  Google Scholar 

  10. A. Dainotti, A. Pescape, K.C. Claffy, Issues and future directions in traffic classification. IEEE Netw. 26(1), 35–40 (2012)

    Article  Google Scholar 

  11. S. George, S. Kim, S. Shah, J. Hasler, M. Collins, F. Adil, R, Wunderlich, S. Nease, S. Ramakrishnan, A programmable and configurable mixed-mode FPAA SoC. IEEE Trans. Very Large Scale Integr. 24(6), 2253–2261 (2016)

    Google Scholar 

  12. J. Hasler, Opportunities in physical computing driven by analog realization, in IEEE ICRC, San Diego (2016)

    Google Scholar 

  13. J. Hasler, Analog Abstraction, Computation, and Numerical Analysis. Accepted to ISCAS 2018, Florance, May 2018

    Google Scholar 

  14. J. Hasler, B. Marr, Finding a roadmap to achieve large neuromorphic hardware systems. Front. Neuromorphic Eng. (2013), 1–29. https://doi.org/10.3389/fnins.2013.00118

  15. J. Hasler, S. Shah, SoC FPAA hardware implementation of a VMM+WTA embedded learning classifier, in IEEE ECAS (2018)

    Google Scholar 

  16. J. Hasler, S. Shah, Security implications for ultra-low power configurable SoC FPAA embedded systems. J. Low-Power Electron. Appl. 8(2), 1–18 (2018)

    Article  Google Scholar 

  17. P. Hasler, C. Diorio, B.A. Minch, C.A. Mead, Single transistor learning synapses, in Advances in Neural Information Processing Systems, ed. by G. Tesauro, D.S. Touretzky, T.K. Leen, vol. 7 (MIT Press, Cambridge, 1994), pp. 817–824

    Google Scholar 

  18. P. Hasler, C. Diorio, B. Minch, C. Mead, Single transistor learning synapse with long term storage. IEEE Int. Symp. Circuits Syst. 3, 1660–1663 (1995)

    Google Scholar 

  19. P. Hasler, B. Minch, C. Diorio, Adaptive circuits using pFET floating-gate devices, in Advanced Research in VLSI (1999), pp. 215–229

    Google Scholar 

  20. J. Hasler, S. Kim, F. Adil, Scaling floating-gate devices predicting behavior for programmable and configurable circuits and systems. J. Low Power Electron. Appl. 6(3), 13 (2016)

    Article  Google Scholar 

  21. J. Hasler, A. Natarajan, S. Shah, S. Kim, SoC FPAA immersed junior level circuits course, in MSE (2017)

    Google Scholar 

  22. T. Heer, O. Garcia-Morchon, R. Hummen, S.L. Keoh, S.S. Kumar, K. Wehrle, Security challenges in the IP-based internet of things? Wirel. Pers. Commun. 61(3), 527–542 (2011)

    Article  Google Scholar 

  23. Z. Khorshidpour, S. Hashemi, A. Hamzeh, Learning a secure classifier against evasion attack, in IEEE Data Mining Workshops (2016), pp. 295–302

    Google Scholar 

  24. S. Kim, J. Hasler, S. George, Integrated floating-gate programming environment for system-level ICs. EEE Trans. Very Large Scale Integr. 24(6), 2244–2252 (2016)

    Google Scholar 

  25. S. Kim, S. Shah, J. Hasler, Calibration of floating-gate SoC FPAA system. IEEE Trans. Very Large Scale Integr. (2017)

    Google Scholar 

  26. J. King, A.I. Awad, A distributed security mechanism for resource-constrained IoT devices. Informatica 40, 133–143 (2016)

    Google Scholar 

  27. C. Mead, Neuromorphic electronic systems. Proc. IEEE 78, 1629–1636 (1990)

    Article  Google Scholar 

  28. N. Muthumeenakshi, S. Sharma, M. Farjanaaameera, R. Rajaprabha, LSI design of low cost (PUF) physical unclonable function using FPGA and highly secured clock network. IOSR J. VLSI Signal Process. 4(1), 16–21 (2014)

    Article  Google Scholar 

  29. G. Oikonomou, I. Phillips, Experiences from porting the Contiki operating system to a popular hardware platform, in IEEE DCOSS Workshop, Barcelona (2011)

    Google Scholar 

  30. T. Omrani, A. Dallali, B.C. Rhaimi, J. Fattahi, Fusion of ANN and SVM classifiers for network attack detection, in Sciences and Techniques of Automatic Control (2018)

    Google Scholar 

  31. R. Roman, P. Najera, J. Lopez, Securing the Internet of Things. IEEE Comput. 44(9), 51–58 (2011)

    Article  Google Scholar 

  32. T. Saha, V. Sehwag, TV-PUF : a fast lightweight analog physical unclonable function, in IEEE Nanoelectric and Information Systems (2016)

    Google Scholar 

  33. C. Schlottmann, S. Shapero, S. Nease, P. Hasler, A digitally enhanced dynamically reconfigurable analog platform for low-power signal processing. IEEE J. Solid-State Circuits 47(9), 2174–2184 (2012)

    Article  Google Scholar 

  34. P. Velan, M. Cermak, P. Celeda, M. Drasar, A survey of methods for encrypted traffic classification and analysis. Int. J. Netw. Manage. 25(5), 355–374 (2014)

    Article  Google Scholar 

  35. Z. Wang, The applications of deep learning on traffic identification

    Google Scholar 

  36. Z. Wang, Y. Chen, A. Patil, J. Jayabalan, X. Zhang, C.H. Chang, A. Basu, Current mirror array: a novel circuit topology for combining physical unclonable function and machine learning, in IEEE TCAS I (2017)

    Google Scholar 

  37. T. Xu, M. Potkonjak, Robust and flexible FPGA-based digital PUF, in FPL (2014)

    Google Scholar 

Download references

Acknowledgements

This chapter resulted from a conference on IoT and embedded network device security in Paris in July 2017. My first exposure to security of embedded network devices started in Paris, not too far from the conference in 2017, when I (J. Hasler) visited Francois Bayen and his family in Paris in 1991 as a young graduate student. We had a number of technical discussions on embedded integrated circuit (IC) security related to a number of his European projects. These discussions gave me the background and interest to dig deeper in these areas when the time came; I am thankful for everything I learned from him during that visit and later visits. Twenty-six years later these discussions have come full circle. Writing this chapter on security of embedded devices, particularly FPAA devices, has brought me back to the knowledge source. Their family has remained close friends with my family to this day.

Author information

Authors and Affiliations

  1. Georgia Institute of Technology, Atlanta, GA, USA

    Jennifer Hasler

Authors
  1. Jennifer Hasler
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jennifer Hasler .

Editor information

Editors and Affiliations

  1. Ä°stinye University, Ä°stanbul, Turkey

    Çetin Kaya Koç

  2. Nanjing University of Aeronautics and Astronautics, Nanjing, China

    Çetin Kaya Koç

  3. University of California Santa Barbara, Santa Barbara, CA, USA

    Çetin Kaya Koç

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Switzerland AG

About this chapter

Cite this chapter

Hasler, J. (2018). Embedded Classifiers for Energy-Constrained IoT Network Security. In: Koç, Ç.K. (eds) Cyber-Physical Systems Security. Springer, Cham. https://doi.org/10.1007/978-3-319-98935-8_14

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-98935-8_14

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-98934-1

  • Online ISBN: 978-3-319-98935-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics