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Area Targeted Minimization Method of Finite State Machines for FPGA Devices

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Computer Information Systems and Industrial Management (CISIM 2018)

Part of the book series: Lecture Notes in Computer Science ((LNISA,volume 11127))

Abstract

A new method for the minimization of finite state machines (FSMs) is proposed. In this method, such optimization criterion as the number of used logic elements is taken into account already at the stage of minimizing internal states. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found, and the pair that best satisfies the optimization criteria is chosen for merging. In addition, the proposed method allows one to minimize the number of transitions and input variables of the FSM. The binary, one-hot and JEDI state assignment methods are used. Experimental results show, that the used FPGA area is less on average by 18% comparing to traditional methods.

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Acknowledgements

The research has been done in the framework of the grant S/WI/3/2018 and financed from the funds for science by MNiSW.

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Authors and Affiliations

  1. Bialystok University of Technology, Bialystok, Poland

    Adam Klimowicz

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  1. Adam Klimowicz
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Correspondence to Adam Klimowicz .

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Editors and Affiliations

  1. Bialystok University of Technology, Bialystok, Poland

    Khalid Saeed

  2. Warsaw University of Technology, Warsaw, Poland

    Władysław Homenda

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Klimowicz, A. (2018). Area Targeted Minimization Method of Finite State Machines for FPGA Devices. In: Saeed, K., Homenda, W. (eds) Computer Information Systems and Industrial Management. CISIM 2018. Lecture Notes in Computer Science(), vol 11127. Springer, Cham. https://doi.org/10.1007/978-3-319-99954-8_31

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  • DOI: https://doi.org/10.1007/978-3-319-99954-8_31

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-99953-1

  • Online ISBN: 978-3-319-99954-8

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