Abstract
This contribution defines systolic digit-serial architectures for fields G(p m). These architectures are scalable in the sense that their instantiations support multiplication in different fields GF(p m) for which p is fixed and m is variable. These features make the multiplier architectures suitable for ASIC as well as FPGA implementations. In addition, the same architectures are easily applicable to tower fields GF(q m) for a given ground field GF(q), where q itself is a prime power. We simulated the basic cell of a systolic LSDE multiplier on 0.18 μm CMOS technology to verify the functionality of the architectures. Finally, we provide specific values for GF(2m) and GF(3m) fields which are of particular interest in recent cryptographic applications, for example, the implementation of short signature schemes based on the Tate pairing.
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References
Bailey, D.V., Paar, C.: Optimal Extension Fields for Fast Arithmetic in Public-Key Algorithms. In: Krawczyk, H. (ed.) CRYPTO 1998. LNCS, vol. 1462, pp. 472–485. Springer, Heidelberg (1998)
Barreto, P.S.L.M., Kim, H.Y., Lynn, B., Scott, M.: Efficient Algorithms for Pairing-Based Cryptosystems. In: Yung, M. (ed.) CRYPTO 2002. LNCS, vol. 2442, pp. 354–368. Springer, Heidelberg (2002)
Bertoni, G., Guajardo, J., Kumar, S., Orlando, G., Paar, C., Wollinger, T.: Efficient GF(pm) Arithmetic Architectures for Cryptographic Applications. In: Joye, M. (ed.) CT-RSA 2003. LNCS, vol. 2612, pp. 158–175. Springer, Heidelberg (2003)
Blum, T., Paar, C.: High radix Montgomery modular exponentiation on re-configurable hardware. IEEE Transactions on Computers 50(7), 759–764 (2001)
Boneh, D., Franklin, M.: Identity-Based Encryption from the Weil Pairing. In: Kilian, J. (ed.) CRYPTO 2001. LNCS, vol. 2139, pp. 213–229. Springer, Heidelberg (2001)
Frecking, W.L., Parhi, K.K.: Performance-Scalable Array Architectures for Modular Multiplication. In: IEEE International Conference on Application-Specific Systems, Architectures, and Processors — ASAP 2000, July 10-12, pp. 149–162 (2000)
Jeong, Y.J., Burleson, W.P.: VLSI array algorithms and architectures for RSA modular multiplication. IEEE Transactions on VLSI Systems 5(2), 211–217 (1997)
Koblitz, N.: An elliptic curve implementation of the finite field digital signature algorithm. In: Krawczyk, H. (ed.) CRYPTO 1998. LNCS, vol. 1462, pp. 327–337. Springer, Heidelberg (1998)
Koç, Ç.K., Hung, C.Y.: Bit-level systolic arrays for modular multiplication. Journal of VLSI Signal Processing 3(3), 215–223 (1991)
Kornerup, P.: A systolic, linear-array multiplier for a class of right-shift algorithms. IEEE Transactions on Computers 43(8), 892–898 (1994)
Mihăilescu, P.: Optimal Galois Field Bases which are not Normal. In: Biham, E. (ed.) FSE 1997. LNCS, vol. 1267, Springer, Heidelberg (1997)
Page, D., Smart, N.P.: Hardware implementation of finite fields of characteristic three. In: Kaliski Jr., B.S., Koc, C.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 529–539. Springer, Heidelberg (2003)
Smart, N.: Elliptic Curve Cryptosystems over Small Fields of Odd Characteristic. Journal of Cryptology 12(2), 141–151 (1999)
Song, L., Parhi, K.K.: Low energy digit-serial/parallel finite field multipliers. Journal of VLSI Signal Processing 19(2), 149–166 (1998)
Tenca, A.F., Koç, Ç.K.: A Scalable Architecture for Montgomery Multiplication. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 94–108. Springer, Heidelberg (1999)
Tsai, W.C., Shung, C.B., Wang, S.J.: Two systolic architectures for modular multiplication. IEEE Transactions on VLSI Systems 8(1), 103–110 (2000)
Walter, C.D.: Systolic Modular Multiplication. IEEE Transactions on Computers 42(3), 376–378 (1993)
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Bertoni, G., Guajardo, J., Orlando, G. (2003). Systolic and Scalable Architectures for Digit-Serial Multiplication in Fields GF(p m). In: Johansson, T., Maitra, S. (eds) Progress in Cryptology - INDOCRYPT 2003. INDOCRYPT 2003. Lecture Notes in Computer Science, vol 2904. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24582-7_26
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DOI: https://doi.org/10.1007/978-3-540-24582-7_26
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