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Operation Reuse on Handheld Devices

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Languages and Compilers for Parallel Computing (LCPC 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2958))

Abstract

Compilers have long used redundancy removal to improve program execution speed. For handheld devices, redundancy removal is particularly attractive because it improves execution speed and energy efficiency at the same time. In a broad view, redundancy exists in many different forms, e.g., redundant computations and redundant branches. We briefly describe our recent efforts to expand the scope of redundancy removal. We attain computation reuse by replacing a code segment by a table look-up. We use IF-merging to merge conditional statements into a single conditional statement. We present part of our preliminary experimental results from an HP/Compaq iPAQ PDA.

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References

  1. Huang, J., Lilja, D.: Exploiting basic block value locality with block reuse. In: The 5th Int. Symp. on High-Performance Computer Architecture (1999)

    Google Scholar 

  2. Huang, J., Lilja, D.: Balancing reuse opportunities and performance gains with sub-block value reuse. Technical Report, University of Minnesota (2002)

    Google Scholar 

  3. Sastry, S., Bodik, R., Smith, J.: Characterizing coarse-grained reuse of computation. In: 3rd ACM Workshop on Feedback Directed and Dynamic Optimization (2000)

    Google Scholar 

  4. Sodani, A., Sohi, G.: Dynamic instruction reuse. In: Proc. of the 24th Int. Symp. on Computer Architecture, pp. 194–205 (1997)

    Google Scholar 

  5. Citron, D., Feitelson, D.: Hardware memoization of mathematical and trigonometric functions. Technical Report, Hebrew University of Jerusalem (2000)

    Google Scholar 

  6. Connors, D., Hunter, H., Cheng, B., Hwu, W.: Hardware support for dynamic activation of compiler-directed computation reuse. In: Proc. of the 9th Int. Conf. on Architecture Support for Programming Languages and Operating Systems (2000)

    Google Scholar 

  7. Connors, D., Hwu, W.: Compiler-directed dynamic computation reuse: Rationale and initial results. In: Proc. of 32nd Int. Symp. on Microarchitecture, pp. 158–169 (1999)

    Google Scholar 

  8. Michie, D.: Memo functions and machine learning. Nature 218, 19–22 (1968)

    Article  Google Scholar 

  9. Richardson, S.: Exploiting trivial and redundant computation. In: Proc. of the 11th Symp. on Computer Arithmetic, pp. 220–227 (1993)

    Google Scholar 

  10. Calder, B., Feller, P., Eustace, A.: Value profiling. In: Proc. of the 30th Int. Symp. on Microarchitecture, pp. 259–269 (1997)

    Google Scholar 

  11. Intel Strong ARM SA-1110 Microprocessor Developer’s Manual (2001)

    Google Scholar 

  12. Lee, C., Potkonjak, M., Mangione-Smith, W.: Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In: Proc. of the 30th Int. Symp. on Microarchitecture, pp. 330–335 (1997)

    Google Scholar 

  13. Guthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R.: Mibench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization, pp. 3–14 (2001)

    Google Scholar 

  14. Sodani, A., Sohi, G.: Understanding the differences between value prediction and instruction reuse. In: Proc. of the 31th Int. Symp. on Computer Architecture, pp. 205–215 (1998)

    Google Scholar 

  15. Bodik, R., Gupta, R., Soffa, M.: Interprocedural conditional branch elimination. In: Proc. of the Conference on Programming Language Design and Implementation (1997)

    Google Scholar 

  16. Kreahling, W., Whalley, D., Bailey, M., Yuan, X., Uh, G., Engelen, R.: Branch elimination via multi-variable condition merging. In: Proc. of the European Conference on Parallel and Distributed Computing (2003)

    Google Scholar 

  17. Yang, M., Uh, G., Whalley, D.: Efficient and effective branch reordering using profile data. Trans. on Programming Languages and Systems 24 (2002)

    Google Scholar 

  18. Ball, T., Larus, J.: Branch prediction for free. In: Proc. of the Conference on Programming Language Design and Implementation (1993)

    Google Scholar 

  19. Smith, J.: A study of branch prediction strategies. In: Proc. of the 4th International Symposium on Computer Architecture (1981)

    Google Scholar 

  20. Park, J., Schlansker, M.: On predicated execution. Technical Report. HPL-91-58, Hewlett Packard Laboratories (1991)

    Google Scholar 

  21. Sias, J., August, D., Hwu, W.: Accurate and efficient predicate analysis with binary decision diagrams. In: Proc. of the 33rd International Symposium on Microarchitecture (2000)

    Google Scholar 

  22. Calder, B., Grunwald, D.: Reducing branch costs via branch alignment. In: Proc. of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (1994)

    Google Scholar 

  23. Mueller, F., Whalley, D.: Avoiding conditional branches by code replication. In: Proc. of the Conference on Programming Language Design and Implementation (1995)

    Google Scholar 

  24. Parikh, D., Skadron, K., Zhang, Y., Barcella, M., Stan, M.: Power issues related to branch prediction. In: Proc. of the 8th International symposium on High-Performance Computer Architecture (2002)

    Google Scholar 

  25. Hennessy, J., Patterson, D.: Computer architecture: A quantitative approach, 2nd edn. Morgan Kaufmann, San Francisco

    Google Scholar 

  26. Wu, Y., Lee, Y.: Comprehensive redundant load elimination for the ia-64 architecture. In: Carter, L., Ferrante, J. (eds.) LCPC 1999. LNCS, vol. 1863, p. 53. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  27. Hind, M., Burke, M., Carini, P., Choi, J.: Interprocedural pointer alias analysis. ACM Trans. on Programming Languages and Systems 21 (1999)

    Google Scholar 

  28. Simpson, T.: Global value numbering. Technical report, Rice University (1994)

    Google Scholar 

  29. Wolfe, M.: High performance compilers for parallel computing. Addison-Wesley Publishing Company, Reading (1996)

    MATH  Google Scholar 

  30. Ball, T., Larus, J.: Efficient path profiling. In: Proc. of the 29th International Symposium on Microarchitecture (1996)

    Google Scholar 

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Ding, Y., Li, Z. (2004). Operation Reuse on Handheld Devices. In: Rauchwerger, L. (eds) Languages and Compilers for Parallel Computing. LCPC 2003. Lecture Notes in Computer Science, vol 2958. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24644-2_18

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  • DOI: https://doi.org/10.1007/978-3-540-24644-2_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-21199-0

  • Online ISBN: 978-3-540-24644-2

  • eBook Packages: Springer Book Archive

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