Skip to main content

Design of AES Based on Dual Cipher and Composite Field

  • Conference paper
Topics in Cryptology – CT-RSA 2004 (CT-RSA 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2964))

Included in the following conference series:

Abstract

Recently, Barkan and Biham proposed the concept of dual ciphers and pointed out that there are 240 dual ciphers of AES (Dual AES). An interesting application of dual ciphers is to design a cipher which run faster than the original cipher. In this paper, we first generalize the dual AES and propose a complete setup procedure to determine all dual ciphers. Then, a hardware implementation of AES based on the combination of dual cipher and composite field is proposed. We demonstrate that our AES design not only offers better performance and smaller area requirement than the design proposed by Wolkerstorfer et al which uses a composite field only. Our results confirm Barkan et al.’s conjecture that it is possible to design an AES cipher more efficiency than ever.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. National Institute of Standards and Technology (NIST). Advanced Encryption Standard (AES). FIPS Publication 197 (November 2001), Available at http://csrc.nist.gov/encryption/aes/index.html

  2. Barkan, E., Biham, E.: In How Many Ways Can You Write Rijndael. In: Zheng, Y. (ed.) ASIACRYPT 2002. LNCS, vol. 2501, pp. 160–175. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  3. Rudra, P., Dubey, C., Jutla, V., Kumar, J., Rao, P.: Efficient Rijndael Encryption Implementation with Composite Field Arithmetic. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 171–184. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  4. Wolkerstorfer, J., Oswald, E.: An ASIC Implementation of the AES Sboxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, pp. 67–78. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  5. Ichikawa, T., Kasuya, T., Matsui, M.: Hardware Evaluation of the AES Finalists. In: The Third Advanced Encryption Standard Candidate Conference, pp. 279–285 (2000), , Available at http://csrc.nist.gov/encryption/aes/round2/conf3/papers/15-tichikawa.pdf

  6. Kua, H., Verbauwhede, I.: Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 51–64. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  7. Satoh, S., Morioka, K.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  8. McLoone, M., et al.: High performance single-chip FPGA Rijndael algorithm implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 65–76. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  9. Morioka, S., Satoh, A.: An Optimized S-Box Circuit Architecture for Low Power AES Design. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 172–186. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  10. Daemen, J., Rijmen, V.: The Design of Rijndael. Springer printed in Germany (2002)

    Google Scholar 

  11. Lidl, R., Niederreiter, H.: Introduction to finite fields and their applications. Cambridge University Press, Cambridge (1986)

    MATH  Google Scholar 

  12. MacWilliams, F.J., Sloane, N.J.A.: The Theory of Error-Correcting Codes. North- Holland Publishing Company, Amsterdam (1978)

    Google Scholar 

  13. Paar, C.: Efficient VLSI Architectures for Bit Parallel Computation in Galois Fields. PhD Thesis, Institute for Experimental Mathematics, University of Essen, Germany (1994)

    Google Scholar 

  14. Rijmen, V.: Efficient Implementation of the Rijndael S-box, Available at http://www.esat.kuleuven.ac.be/rijmen/rijndael

  15. Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., Legat, J.-D.: Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. Accepted at Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003) (September 2003)

    Google Scholar 

  16. Chen, K.Y., Chen, P.D., Laih, C.S.: Speed up AES with the modification of shift row table. Public Comments on the Draft Federal Information Processing Standard ( FIPS ) (2001)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Wu, SY., Lu, SC., Laih, C.S. (2004). Design of AES Based on Dual Cipher and Composite Field. In: Okamoto, T. (eds) Topics in Cryptology – CT-RSA 2004. CT-RSA 2004. Lecture Notes in Computer Science, vol 2964. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24660-2_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-24660-2_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20996-6

  • Online ISBN: 978-3-540-24660-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics