Abstract
The paper presents new architectural solutions for parallel systems built of run-time configurable shared memory processor clusters. The proposed architecture enables run-time switching of processors between clusters combined with parallel data transfers to processors that is called communication on the fly. Programs are executed according to cache controlled macro data flow paradigm. An extended macro-data flow graph representation is introduced that includes modeling of program execution control in the system. Programs can be optimized based on decomposition onto dynamic SMP clusters and the use of communication on the fly. Simulation results show potential of the proposed system architecture for execution of fine grain numerical parallel programs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Protic, J., Tomasevic, M., Milutinovic, V.: A Survey of Shared Memory Systems. In: Proc. of the 28th Annual Hawaii International Conference of System Sciences, Maui, Hawai, January 1995, pp. 74–84 (1995)
Sima, D., Fountain, T., Kacsuk, P.: Advanced Computer Architectures; A Design Space Approach. Addison-Wesley, Reading (1997)
Kanaka, Y., Matsuda, M., Ando, M., Kazuto, K., Sato, M.: COMPaS: A Pentium Pro PC-based SMP Cluster and its Experience. In: Rolim, J.D.P. (ed.) IPPS-WS 1998 and SPDP-WS 1998. LNCS, vol. 1388, pp. 486–497. Springer, Heidelberg (1998)
Kanaka, Y., Matsuda, M., Ando, M., Kazuto, K., Sato, M.: Performance Improvement by Overlapping Computation and Communication on SMP Clusters. In: Int’l Conference on PDPTA 1998, vol. 1, pp. 275–282 (1998)
Pentium Pro Cluster Workshop, http://www.scl.ameslab.gov/workshops/
Ikedo, T., Yamada, J., Nonoyama, Y., Kimura, J., Yoshida, M.: An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network. In: 2nd Aizu Int’l Symp. on Parallel Algorithms/Architecture Synthesis, Aizu-Wakamatsu, March 1997, pp. 50–57 (1997)
Scalable Clusters of Commodity Computers, http://www.csag.cs.uiuc.edu/projects/clusters.html
Multimax Technical Summary, Encore Computer Summary (March 1987)
Lenoski, D., et al.: The Stanford Dash multi-processor. IEEE Computer 25(3), 63–79 (1992)
Convex Exemplar Architecture. Convex Press, p. 239 (1994)
Milenkovic, A., Milutinovic, V.: Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs. In: Bode, A., Ludwig, T., Karl, W.C., Wismüller, R. (eds.) Euro-Par 2000. LNCS, vol. 1900, pp. 558–566. Springer, Heidelberg (2000)
Tudruj, M., Masko, L.: Program Execution Control for Communication on the Fly in Dynamic Shared Memory Processor Clusters. In: Int. Conf. on Parallel Comp. in Electric. Eng., PARELEC 2002, Warsaw, September 2002, pp. 15–20. IEEE Comp. Society Press, Los Alamitos (2002)
Tudruj, M., Masko, L.: Communication on the Fly and Program Execution Control in a System of Dynamically Configurable SMP Clusters. In: 11-th Euromicro Conference on Parallel Distributed and Network-Based Processing, Genoa – Italy, February 2003, pp. 67–74. IEEE Comp. Society Press, Los Alamitos (2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tudruj, M., Masko, L. (2004). Communication on the Fly in Dynamic SMP Clusters – Towards Efficient Fine Grain Numerical Computations. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2003. Lecture Notes in Computer Science, vol 3019. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24669-5_8
Download citation
DOI: https://doi.org/10.1007/978-3-540-24669-5_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-21946-0
Online ISBN: 978-3-540-24669-5
eBook Packages: Springer Book Archive