Skip to main content

Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time Embedded Systems

  • Conference paper
Real-Time and Embedded Computing Systems and Applications (RTCSA 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2968))

Abstract

A cycle-stealing DMA I/O task proceeds by stealing bus cycles from the CPU . The execution time of the DMA I/O task depends on the sequence of CPU instructions executing concurrently with it. This paper presents a method for bounding the worst-case execution time of a cycle-stealing DMA I/O task executing concurrently with a set of CPU tasks on a single-processor system. Our method uses the dynamic-programming technique to minimize the computational cost. We conducted exhaustive simulations on a widely-used embedded controller. The experimental results demonstrate our method safely and tightly bounds the worst-case execution times of cycle-stealing DMA I/O tasks.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. MC68030 Enhanced 32-bit Microprocessor: User’s Manual. Motorola (1987)

    Google Scholar 

  2. Engblom, J., Ermedah, A.: Modeling complex flows for worst-case execution time analysis. In: Proceedings of the 21th Real-Time System Symposium, November 2000, pp. 163–174 (2000)

    Google Scholar 

  3. Healy, C., Arnold, R., Muller, F., Whalley, D., Harmon, M.: Bounding pipeline and instruction cache performance. IEEE Transactions on Computers 48(1), 53–70 (1999)

    Article  Google Scholar 

  4. Huang, T.-Y., Liu, J.W.-S.: Predicting the worst-case execution time of the concurrent execution of instructions and cycle-stealing DMA I/O operations. ACM SIGPLAN Notices 30(11) (November 1995)

    Google Scholar 

  5. Jeffay, K., Stanat, D.F., Martel, C.U.: On non-preemptive scheduling of periodic and sporadic tasks. In: Proceedings of the 12th Real-Time System Symposium, pp. 129–139 (1991)

    Google Scholar 

  6. Kim, S.-K., Ha, R., Min, S.L.: Analysis of the impacts of overestimation sources on the accuracy of worst case timing analysis. In: Proceedings of the 20th Real-Time System Symposium, December 1999, pp. 22–31 (1999)

    Google Scholar 

  7. Klein, M.H., Ralya, T.: An anlysis of input/output paradigms for realtime systems. Technical Report CMU/SEI-90-TR-19, CMU Software Engineering Institute (July 1990)

    Google Scholar 

  8. Li, Y.-T.S., Malik, S.: Performance analysis of embedded software using implicit path enumeration. In: Proceedings of the 32nd ACM/IEEE Design Automation Conference, June 1995, pp. 456–561 (1995)

    Google Scholar 

  9. Lim, S.-S., Han, J.H., Kim, J., Min, S.L.: A worst case timing analysis technique for multiple-issue machines. In: Proceedings of the 19th Real-Time System Symposium, December 1998, pp. 334–345 (1998)

    Google Scholar 

  10. Liu, C.L., Layland, J.: Scheduling algorithms for multiprogramming in a hard real-time environment. Journal of the ACM 10(1), 46–61 (1973)

    Article  MathSciNet  Google Scholar 

  11. Muller, F., Whalley, D., Harmon, M.: Predicting instruction cache behavior. In: ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems (June 1994)

    Google Scholar 

  12. Park, C.-Y., Shaw, A.C.: Experiments with a program timing tool based on source-level timing schema. IEEE Computer 48, 48–57 (1991)

    Google Scholar 

  13. Sha, L., Rajkumar, R., Lehoczky, J.P.: Priority inheritance protocols: An approach to real-time synchronization. IEEE Transactions on Computers 39(9), 1175–1185 (1990)

    Article  MathSciNet  Google Scholar 

  14. Theiling, H., Ferdinand, C.: Combining abstract interpretation and ILP for microarchitecture modelling and program path analysis. In: Proceedings of the 19th Real-Time System Symposium, pp. 144–153 (December 1998)

    Google Scholar 

  15. Vrchoticky, A., Puschner, P.: On the feasibiity of response time predictions– an experimental evaluation. Technical Report 2/91, Institute fur Technische Informatik Technische Universitat Wien (March 1991)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Huang, TY., Chou, CC., Chen, PY. (2004). Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time Embedded Systems. In: Chen, J., Hong, S. (eds) Real-Time and Embedded Computing Systems and Applications. RTCSA 2003. Lecture Notes in Computer Science, vol 2968. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24686-2_31

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-24686-2_31

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-21974-3

  • Online ISBN: 978-3-540-24686-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics