Abstract
This paper proposes a formal design representation model, called Operation Net System, for high-level synthesis of asynchronous systems which is based on transformational approaches. Operation Net System consists of Operation Net, which is based on hierarchical timed Petri nets, and a module graph to unify the description of control and data parts of an asynchronous system. It is used as an intermediate design representation during transformations. Several semantic-preserving basic transformations are defined and used to successively transform an initial design representation into an optimized implementation satisfying designer’s requirements. The hierarchical concept of Operation Net reduces the complexity of net operations such as finding the relation of two operations by hiding sub-hierarchical blocks. The selection of the basic transformations is guided by an exploration strategy which performs operation scheduling, resource allocation, and module binding simultaneously. To deal with the complexity of the exploration, we use an iterative algorithm such as Tabu search. This integration of high-level synthesis sub-tasks enables designers to get a better chance to reach a globally optimized solution.
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Rotem, S., Stevens, K., Ginosar, R., Beerel, P., Myers, C., Yun, K., Kol, R., Dike, C., Roncken, M., Agapiev, B.: RAPPID: An asynchronous instruction length decoder. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 60–70 (1999)
Martin, A.J.: Programming in VLSI: From communicating processes to delayinsensitive circuits. In: Hoare, C.A.R. (ed.) Developments in Concurrency and Communication. UT Year of Programming Series, pp. 1–64. Addison-Wesley, Reading (1990)
Brunvand, E.: Translating Concurrent Communicating Programs into Asynchronous Circuits. PhD thesis, Carnegie Mellon University (1991)
Berkel, K.v.: Handshake Circuits: an Asynchronous Architecture for VLSI Programming. International Series on Parallel Computation, vol. 5. Cambridge University Press, Cambridge (1993)
Peeters, A.M.G.: Single-Rail Handshake Circuits. PhD thesis, Eindhoven University of Technology (1996)
Akella, V., Gopalakrishnan, G.: SHILPA: A high-level synthesis system for selftimed circuits. In: Proc. International Conf. Computer-Aided Design (ICCAD), pp. 587–591. IEEE Computer Society Press, Los Alamitos (1992)
Jacobson, H., Brunvand, E., Gopalakrishnan, G., Kudva, P.: High-level asynchronous system design using the ACK framework. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 93–103. IEEE Computer Society Press, Los Alamitos (2000)
Kessels, J., Marston, P.: Designing asynchronous standby circuits for a low-power pager. Proceedings of the IEEE 87, 257–267 (1999)
Yoo, D.H., Lee, D.I.: Translating concurrent programs into speed-independent circuits through petri net transformations. IEICE Transactions on Fundamentals E83-A, 2203–2211 (2000)
Glover, F.: Tabu search - Part I. ORSA Journal on Computing 1, 190–206 (1989)
Glover, F.: Tabu search - Part II. ORSA Journal on Computing 2, 4–32 (1989)
Badia, R.M., Cortadella, J.: High-level synthesis of asynchronous systems: Scheduling and process synchronization. In: Proc. European Conference on Design Automation (EDAC), pp. 70–74. IEEE Computer Society Press, Los Alamitos (1993)
Bachman, B.M.: Architectural-level synthesis of asynchronous systems. Master’s thesis, The University of Utah (1998)
Peng, Z., Kuchcinski, K.: Automated transformation of algorithms into register– transfer level implementations. IEEE Transactions on Computer-Aided Design 13 (1994)
Eles, P., Kuchcinski, K., Peng, Z.: System Synthesis with VHDL. Kluwer Academic Publishers, Dordrecht (1999)
Chu, T.A.: Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT (1987)
Micheli, G.D.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)
Murata, T.: Petri nets: Properties, analysis, applications. Proceedings of the IEEE 77, 541–580 (1989)
Kim, E., Lee, J.G., Lee, D.I.: Automatic process-oriented control circuit generation for asynchronous high-level synthesis. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 104–113. IEEE Computer Society Press, Los Alamitos (2000)
Theobald, M., Nowick, S.M.: Transformations for the synthesis and optimization of asynchronous distributed control. In: Proc. ACM/IEEE Design Automation Conference (2001)
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Yoo, DH., Lee, DI., Lee, JA. (2004). Operation Net System: A Formal Design Representation Model for High-Level Synthesis of Asynchronous Systems Based on Transformations. In: Cortadella, J., Reisig, W. (eds) Applications and Theory of Petri Nets 2004. ICATPN 2004. Lecture Notes in Computer Science, vol 3099. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27793-4_25
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DOI: https://doi.org/10.1007/978-3-540-27793-4_25
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