Abstract
The microprocessor is a crucial component of a reliable system. With improvement in semiconductor manufacturing, more and more transistors may be integrated into a single chip with increased potential detriment to dependability. Fault-tolerant single-chip multiprocessors offer an ideal architecture for achieving high availability while maintaining high performance. The design of a fault-tolerant single-chip multiprocessor is described – from hardware redundancy to software support and firmware information strategies. The design aims at masking the influences of errors and automatically correcting system states, which differs from traditional approaches which mainly target errors in the memory and I/O subsystems. Dynamic recovery and reconfiguration are also described to provide adequate protection from catastrophic failure of the system.
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© 2004 Springer-Verlag Berlin Heidelberg
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Yao, W., Wang, D., Zheng, W. (2004). A Fault-Tolerant Single-Chip Multiprocessor. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_12
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DOI: https://doi.org/10.1007/978-3-540-30102-8_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
Online ISBN: 978-3-540-30102-8
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