A Two-Level On-Chip Bus System Based on Multiplexers

Abstract

The SoC (System on a Chip) design paradigm becomes a promising way of system integration as the level of design complexity is getting higher. There may be many IP modules to be integrated on a single chip in the modern SoC design. On-chip buses are usually used to interconnect the modules on a chip. Many bus architectures have been proposed for the interconnection of modules on a chip. We propose a two-level on-chip bus system that provides inter-bus transactions with multiplexers rather than with tri-state buffers or MOS switches such as in the segmented bus approaches. Our bus system can maximize the system throughput with concurrent inter-bus transactions as well as intra-bus transactions while preserving the already developed on-chip bus protocols for IP reuse. We present the performance simulation results of our approach with several different configurations compared with the existing segmented bus structures in terms of the total number of bus transactions executed in a given time.