Abstract
Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. The power awareness problem of the reconfigurable array is first proposed in this paper. A heuristic algorithm has been presented for the same. The algorithm is simple but efficient. The performance of the proposed algorithm is more powerful than that of the older algorithm, without loss of harvest.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Leighton, T., Gamal, A.E.: Wafer-scal Integration of Systoric Arrays. IEEE Trans. on Computer 34(5), 448–461 (1985)
Lam, C.W.H., Li, H.F., Jakakumar, R.: A Study of Two Approaches for Reconfiguring Fault-tolerant Systoric Array. IEEE Trans. on Computers 38(6), 833–844 (1989)
Koren, I., Singh, A.D.: Fault Tolerance in VLSI Circuits. Computer 23(7), 73–83 (1990)
Chen, Y.Y., Upadhyaya, S.J., Cheng, C.H.: A Comprehensive Reconfiguration Scheme for Fault-tolerant VLSI/WSI Array Processors. IEEE Trans. on Computers 46(12), 1363–1371 (1997)
Horita, T., Takanami, I.: Fault-tolerant Processor Arrays Based on the 1.5-track Switches with Flexible Spare Distributions. IEEE Trans. on Computers 49(6), 542–552 (2000)
Kuo, S.Y., Fuchs, W.K.: Efficient Spare Allocation for Reconfigurable Arrays. IEEE Design and Test 4(7), 24–31 (1987)
Wey, C.L., Lombardi, F.: On the Repair of Redundant RAM’s. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2), 222–231 (1987)
Zhang, L.: Fault-Tolerant meshes with small degree. IEEE Trans. on Computers 51(5), 553–560 (2002)
Kuo, S.Y., Chen, I.Y.: Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design 11(10), 1289–1300 (1992)
Low, C.P., Leong, H.W.: On the reconfiguration of degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design of integrated circuits and systems 16(10), 1213–1221 (1997)
Low, C.P.: An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. on Computers 49(6), 553–559 (2000)
Jigang, W., Heiko, S., Thambipillai, S.: New architecture and algorithms for degradable VLSI/WSI arrays. In: Ibarra, O.H., Zhang, L. (eds.) COCOON 2002. LNCS, vol. 2387, pp. 181–190. Springer, Heidelberg (2002)
Aho, A.V., Hopcroft, J.E., Ullman, J.D.: The design and analysis of computer algorithms. Addison-Wesley, Reading (1974)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wu, J., Srikanthan, T. (2004). Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_37
Download citation
DOI: https://doi.org/10.1007/978-3-540-30102-8_37
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
Online ISBN: 978-3-540-30102-8
eBook Packages: Springer Book Archive