Abstract
The on-chip memory performance of embedded systems directly affects the system designers’ decision about how to allocate expensive silicon area. We investigate a novel memory architecture, flexible sequential and random access memory (FSRAM), for embedded systems. To realize sequential accesses, small “links” are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buffer (SAB). To evaluate the architecture-level performance of FSRAM, we run the Mediabench benchmark programs [1] on a modified version of the Simplescalar simulator [2]. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%. We also designed RTL and SPICE models of the FSRAM [3], which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In: Proc. of the 30th Annual International Symposium on Microarchitecture (Micro 30) (December 1997)
Burger, D., Austin, T.M.: The simplescalar tool set version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin (June 1997)
Chen, Y., Ranganathan, K., Puthenveetil, A., Bazargan, K., Lilja, D.J.: FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems. Laboratory for Advanced Research in Computing Technology and Compilers Technical Report No. ARCTiC 04-01 (February 2004)
Panda, P.R., Dutt, N.D., Nicolau, A.: Data cache sizing for embedded processor applications. Technical Report TCS-TR-97-31, University of California, Irvine (June 1997)
Panda, P.R., Dutt, N.D., Nicolau, A.: Architectural exploration and optimizatioin of local memory in embedded systems. In: International Symposium on System Synthesis (ISSS 1997), Antwerp (September 1997)
Shiue, W., Chakrabati, C.: Memory Exploration for Low Power Embedded Systems. In: IEEE/ACM Proc.of 36th. Design Automation Conference (DAC 1999) (June 1999)
Moon, J., Athas, W.C., Beerel, P.A., Draper, J.T.: Low-Power Sequential Access Memory Design. In: EEE 2002 Custom Integrated Circuits Conference, June 2002, pp. 741–744 (2002)
Sbeyti, H., Niar, S., Eeckhout, L.: Adaptive Prefetching for Multimedia Applications in Embedded Systems. In: DATE 2004, EDA IEEE, Paris, France, February 16-18 (2004)
Pimentel, D., Hertzberger, L.O., Struik, P., Wolf, P.: Hardware versus Hybrid Data Prefetching in Multimedia Processors: A Case Study. In: The Proc. of the IEEE Int. Performance, Computing and Communications Conference (IPCCC 2000), Phoenix, USA, February 2000, pp. 525–531 (2000)
Zucker, D.F., Flynn, M.J., Lee, R.B.: A Comparison of Hardware Prefetching Techniques For Multimedia Benchfmarks. In: Proceedings of the International Conferences on Multimedia Computing and Systems, Himshima, Japan (June 1996)
De La Luz, V., Kandemir, M., Kolcu, I.: Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems. In: DAC, pp. 213–218 (2002)
Intel corparatin, The intel XScale Microarchitecture technical summary, Technical report (2001)
Smith, J.E., Hsu, W.C.: Prefetching in Supercomputer Instruction Caches. In: Proceedings of Supercomputing 1992, pp. 588–597 (1992)
VanderWiel, S.P., Lilja, D.J.: Data Prefetch Mechanisms. ACM Computing Surveys 32(2), 174–199 (2000)
Lilja, D.J.: Measuring Computer Performance. Cambridge University Press, Cambridge (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Chen, Y., Ranganathan, K., Pai, V.V., Lilja, D.J., Bazargan, K. (2004). Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_8
Download citation
DOI: https://doi.org/10.1007/978-3-540-30102-8_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
Online ISBN: 978-3-540-30102-8
eBook Packages: Springer Book Archive