Abstract
Application Specific Instruction Processors (ASIPs) are increasingly becoming popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop-gradual refinement of processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific instructions and to automatically generate the required software tools (such as instruction set simulator, C-compiler, assembler, profiler etc.) as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor which implements common encryption functionality used in symmetric block cipher algorithms for IPsec. The coprocessor is accessed via shared memory and as a consequence, our approach is easily adaptable to arbitrary processor architectures. In the case study, we used Blowfish as encryption algorithm and a MIPS architecture as main processor.
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Scharwaechter, H. et al. (2004). ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. In: Schepers, H. (eds) Software and Compilers for Embedded Systems. SCOPES 2004. Lecture Notes in Computer Science, vol 3199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30113-4_4
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DOI: https://doi.org/10.1007/978-3-540-30113-4_4
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