Abstract
The paper presents a hybrid architecture for digital polar-to-Cartesian (i.e. phase-to-I/Q) designs. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources. FPGA resource utilization, timing and power consumption as well as accuracy of calculated results may be optimised consistently in comparison to conventional pure CORDIC algorithm implementations.
This work was supported by the German Federal Ministry of Education and Research under contract FKZ17 103 03.
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Janiszewski, I., Meuth, H., Hoppe, B. (2004). FPGA-Efficient Hybrid LUT/CORDIC Architecture. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_102
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DOI: https://doi.org/10.1007/978-3-540-30117-2_102
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