Abstract
Most of Block based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is proposed. Thanks to the use of the on–line arithmetic (OLA) two goal are achieved: it is possible to implement a full 16 × 16 macroblock SAD in a single FPGA device and it permits us to speed up the computation by early truncation of the SAD calculation. Reconfigurable devices allows us to change 8 × 8 or 16 × 16 pixels per block models. Comparison with other related works are provided.
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© 2004 Springer-Verlag Berlin Heidelberg
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Olivares, J., Hormigo, J., Villalba, J., Benavides, I. (2004). Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_112
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DOI: https://doi.org/10.1007/978-3-540-30117-2_112
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
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