Abstract
Very high speed and small area hardware architectures of the Serpent encryption algorithm are presented in this paper. The Serpent algorithm was a submission to the National Institute of Technology (NIST) as a proposal for the Advanced Encryption Standard (FIPS-197). Although it was not finally selected, Serpent was considered very secure and with a high potential in hardware implementations. Among others, a fully pipelined Serpent architecture is described in this paper and when implemented in a Virtex-II X2C2000-6 FPGA device, it runs at a throughput of 40 Gbps.
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Lázaro, J., Astarloa, A., Arias, J., Bidarte, U., Cuadrado, C. (2004). High Throughput Serpent Encryption Implementation. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_114
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DOI: https://doi.org/10.1007/978-3-540-30117-2_114
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