Abstract
Current trends show that in future it will be essential that various kinds of applications are running on one chip. These require an efficient and flexible network on chip which is able to adapt to the demands of supported modules. This makes it necessary to think about what kind of network on chip will meet these requirements. This paper describes an approach for a reconfigurable network on chip which allows adapting the performance and topology at run-time to the demand of the application running on Xilinx FPGA.
This research work is sponsored by the German special research program “Reconfigurable Computing Systems” – SPP 1148 from the Deutsche Forschungsgemeinschaft DFG
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References
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Huebner, M., Ullmann, M., Braun, L., Klausmann, A., Becker, J. (2004). Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_122
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DOI: https://doi.org/10.1007/978-3-540-30117-2_122
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