FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation

Abstract

Phylogenetic tree is a meaningful representation for the evolutionary history of different organisms. Due to the exponentially increasing search space for the optimal Maximum Likelihood (ML) criterion, the phylogeny inference is classified as NP-hard. Heuristic search makes use of the likelihood evaluation function extensively to give score for the candidate solutions. This tree evaluation becomes a critical but computationally demanding task. In this paper, we address the computational issue for the evaluation of a phylogenetic tree under ML criterion, for a given set D of n properly aligned DNA sequences each with l nucleotide sites. We present a high performance field programmable gate arrays (FPGA) implementation for tackling the tree evaluation process in order to speed up the tree reconstruction. An efficient fine-grained parallel design based on the idea of partial likelihood is proposed. It has been shown to be 100 times faster than solely using the software.