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A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals

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Field Programmable Logic and Application (FPL 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

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Abstract

This work presents the design of a dynamically reconfigurable function unit supporting Cyclic Redundancy Checks and Reed-Solomon Codes with different code length. The architecture is designed for the usage in mobile wireless communication systems and is optimized concerning area and power consumption.

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References

  1. Michael Ji, H., Killian, E.: Fast Parallel CRC Algorithm and Implementation on a Configurable Processor. In: IEEE Intern. Conference on Communications, vol. 3 (2002)

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  2. Lee, H., Yu, M.L., Song, L.: VLSI Design of Reed-Solomon Decoder Architectures. In: IEEE Intern. Symposium on Circuits and Systems, vol. 5 (2000)

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  3. Pionteck, T., Staake, T., Stiefmeier, T., Kabulepa, L.D., Glesner, M.: Design of a Reconfigurable AES Encryption/Decryption Engine for Mobile Terminals. In: IEEE International Symposium on Circuits and Systems (2004)

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© 2004 Springer-Verlag Berlin Heidelberg

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Pionteck, T., Stiefmeier, T., Staake, T.R., Glesner, M. (2004). A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_134

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_134

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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