Design and Implementation of the Memory Scheduler for the PC-Based Router

Abstract

This paper deals with a design of a memory scheduler as a part of the Liberouter project.

Nowadays, the majority of the designs of memory schedulers is aimed at providing a high throughput while using a high-capacity DDR SDRAM memory. The memory scheduler is FPGA-based. This allows us to test many versions of the design with real network traffic and to set optimal parameters for the memory scheduler units. For reasons of capacity and throughput we use DDR SDRAM memory. The effective DRAM access time is reduced by overlapping multiple accesses to different banks in a special queue composed of the FPGA embedded Block SelectRAM^TMs.