Abstract
A new procedure for Intellectual Property Protection (IPP) of circuits based on the residue number system (RNS) and implemented over FPL devices is presented. The aim is to protect the author rights in the development and distribution of reusable modules (IP cores) by means of an electronic signature embedded within the design. The presented protection scheme is oriented to circuits based on the RNS but can be easily extended to systems implemented on programmable devices. As an example, a 128-bit signature is introduced into a CIC filter without affecting performance and negligible area increase.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Karhng, A.B., Lach, J., Mangione-Smith, W.H., Mantik, S., Markov, I.L., Potkonjak, M., Tucker, P., Wang, H., Wolfe, G.: Constraint-Based Watermarking Techniques for Design IP Protection. IEEE Transactions on Computer-Aided Design 20(10), 1236–1252 (2001)
Kahng, A.B., Lach, J., Mangione-Smith, W.H., Mantik, S., Markov, I.L., Potkonjak, M., Tucker, P., Wang, H., Wolfe, G.: Watermarking Techniques for Intellectual Property Protection. In: Design Automation Conference, pp. 776–781 (1998)
Rivest, R.L.: The MD5 Message Digest Algorithm. Rivest. Internet RFC 1321 (1992)
Szabo, N.S., Tanaka, R.I.: Residue Arithmetic and its Applications to Computer Technology. McGraw-Hill, New York (1967)
Hamann, V., Sprachmann, M.: Fast Residual Arithmetic with FPGAs. In: Workshop on Design Methodologies for Microelectronics (1995)
Meyer-Bäse, U., Garcia, A., Taylor, F.J.: Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. Journal of VLSI Signal Processing 28(1/2), 115–128 (2001)
Lach, J., Mangione-Smith, W.H., Potkonjak, M.: Fingerprinting Techniques for Field Programmable Gate Array Intellectual Property Protection. IEEE Transactions on Computer-Aided Design 20(10), 1253–1261 (2001)
García, A., Meyer-Bäse, U., Taylor, F.J.: Pipelined Hogenauer CIC Filters Using Field-Programmable Logic and Residue Number System. In: Proc. 1998 IEEE Int. Conf. on Acoustics, Speech and Signal Processing, Seattle, WA, vol. 5, pp. 3085–3088 (May 1998)
Griffin, M., Sousa, M., Taylor, F.: Efficient Scaling in the Residue Number System. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 1075–1078 (1989)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Parrilla, L., Castillo, E., García, A., Lloris, A. (2004). Intellectual Property Protection for RNS Circuits on FPGAs. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_149
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_149
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive