TPR: Three-D Place and Route for FPGAs

Abstract

Due to technology scaling global wires dominate the delay and power budgets, and signal integrity, IR-drops, and process variations pose new design problems. Shrinking time-to-market windows and ever-increasing mask costs have reduced profits alarmingly. In response to the first category of problems, 3D integration can significantly reduce wire-lengths, boost yield, and can particularly be useful for FPGA fabrics because it can address problems related to routing congestion, limited I/O connections, and long wire delays. Practical application of 3D integrated circuits yet needs to gain momentum, partly due to a lack of efficient 3D CAD tools. We propose a new efficient timing-driven partitioning-based placement and routing tool for 3D FPGA integration [1]. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. Finally, the circuit is routed using our 3D detailed routing algorithm. We show that 3D integration results in smaller circuit delays, provided that multi-via lengths are employed between layers or fully buffered routing resources are used. Simulations show on average a total decrease of 25% in wire-length and 35% in delay respectively, over traditional 2D chips, when 8 layers are used in 3D integration.

Cristinel Ababei (Advisor: Professor Kia Bazargan)