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A Specific Scheduling Flow for Dynamically Reconfigurable Hardware

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Field Programmable Logic and Application (FPL 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

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Abstract

Dynamically Reconfigurable Hardware (DRHW) presents the ideal features to cope with the highly dynamic and non-deterministic behaviour of current multimedia applications (such as digital video and 3D games) since it provides both high performance and run-time flexibility. However, in order to take advantage of the DRHW features dynamic task allocation support and scheduling support are needed. Working together, the Interconnection Network (ICN) model for DRHW [1] and the hybrid run-time/design-time scheduling Task Concurrency Management (TCM) scheduling methodology [2] provide the desirable support to use DRHW in embedded systems. First, the ICN model provides support not only for task allocation, but also for inter-task communication, and operating system primitives. Second, TCM provides run-time scheduling support and generates only a small run-time penalty due to its execution because most of the exploration and computation is done at design time.

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References

  1. Marescaux, T., et al.: Interconnection Network enable Fine-Grain Dynamic Multi-Tasking on FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 795–805. Springer, Heidelberg (2002)

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  2. Yang, P., et al.: Energy-Aware Runtime Scheduling for Embedded-Multiprocessors SOCs. IEEE Journal on Design&Test of Computers, 46–58 (2001)

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  3. Resano, J., et al.: Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 585–594. Springer, Heidelberg (2003)

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  4. Resano, J., et al.: A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Elsevier Journal on Microprocessors and Microsystems 28/5-6, 291–301 (2004)

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Author information

Authors and Affiliations

  1. Universidad Complutense de Madrid, Spain

    Javier Resano

Authors
  1. Javier Resano
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Editors and Affiliations

  1. ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  2. University of Paderborn,  

    Marco Platzner

  3. IMEC, Kapeldreef 75, Leuven, Leuven, Belgium

    Serge Vernalde

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© 2004 Springer-Verlag Berlin Heidelberg

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Resano, J. (2004). A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_167

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_167

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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