On Computing Maximum Likelihood Phylogeny Using FPGA

Abstract

Phylogenetic tree (or phylogeny) is a meaningful tree representation for the evolutionary history of different organisms that it has been shown useful in drug discovery, virus identification and functional genomic study [1]. The objective of this project is to develop efficient FPGA implementations for phylogenetic tree reconstruction algorithms. By taking advantage of hardware high-performance, we explore the possibilities of parallelization and system optimization to provide high-speed acceleration for the phylogeny inference. The Maximum Likelihood approach for inferring the phylogeny from molecular data has received much attention [2]. Although the optimal ML phylogenetic tree search problem is classified as NP-hard and it is difficult to find the opti-mal solution, the GAML algorithm (based on Genetic Algorithm and Maxi-mum Likelihood) has been shown to find a good near-optimal solution in rea-sonable time [3]. In [4], we have shown that using HW/SW (Hardware/ Soft-ware) codesign for GAML implementation can provide significant speed-up when compared with software-only implementation. Our HW/SW system has good potential for handling large scale problems in real applications. In [5], an enhanced version of FPGA design with parallel and pipelined implementation for the likelihood evaluation is proposed. It has been shown 100 times faster than the single-CPU solution for the ML tree evaluation. To reduce precision loss attributed to truncation error in the FPGA, we are developing a dynamic floating-point alike structure based on the fixed-point architecture. We have also studied the implementation of phylogenetic tree reconstruction algorithm in the embedded platform (i.e. VirtexII-Pro Platform FPGA). Significant im-provement in data transmission rate between hardware and software and higher clock frequency of FPGA have been realized [6].