Abstract
In this paper, we propose a new area-efficient logic module architecture for SRAM-based FPGAs. This new architecture is motivated by the analysis results of some LUT-level benchmarks. The analysis results indicate that a large percentage of the LUTs in a LUT-level circuit are permutation (P) equivalent (not even including input negations or output negations, called NPN equivalences in the literature, or constant assignments). The proposed logic module utilizes lookup table sharing among two or more basic logic elements (BLEs) in a cluster, as opposed to one LUT per BLE. Preliminary results indicate that almost half of the LUTs are eliminated in all benchmarks. This great area reduction would reflect to the cost and prices of FPGAs and also would strengthen the FPGA usage in applications that have rigid area constraints such as an FPGA within a hearing aid.
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Kocan, F., Meyer, J. (2004). Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_31
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DOI: https://doi.org/10.1007/978-3-540-30117-2_31
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