Abstract
This paper deals with the design and implementation of a frame, time and frequency synchronizer for Hiperlan/2 WLAN standard. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.
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References
ETSI TS 101 475 v1.2.2 BRAN ; HIPERLAN Type 2 ; Physical (PHY)layer
Van Nee, R., Prasad, R.: OFDM for Wireless Multimedia communications. Arctech House, Norwood (2000)
Schmidl, T., Cox, D.: Robust Frequency and Timing Synchronization for OFDM. IEEE Trans. On Comm. 45(12) (December 1997)
Johansson, S., Nilsson, M., Nilsson, P.: An OFDM Timing Synchronization ASIC. In: ICECS 2000. Jounieh, Lebanon (2000)
Almenar, V., Abedi, S., Tafazolli, R.: Synchronization Techniques for HIPERLAN/2. In: VTC 2000 (Fall), Atlantic City, USA (2002)
Fort, A., Weijers, J., Derudder, V., Eberle, W., Bourdoux, A.: A performance and complexity comparison of auto-correlation and cross-correlation for OFDM burst synchronization. In: ICASSP 2003, Hong Kong (2003)
BRAN WG3 PHY Subgroup. Criteria for Comparison. ETSI/BRAN document no. 30701F (1998)
Khun-Jush, J., Malogren, G., Schramm, P., Torsner, J.: HIPERLAN type 2 for broadband wireless communication. Ericsson Review (2), 108–120 (2000)
Cardells, F., Valls, J.: High Performance Quadrature Digital Mixers for FPGA. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, p. 905. Springer, Heidelberg (2002)
Canet, M.J., Vicedo, F., Valls, J., Almenar, V.: Design of a digital front-end transmitter for OFDM-WLAN systems using FPGA. In: ISCCSP 2004, Hammamet, Tunisia (2004)
Heiskala, J., Terry, J.: OFDM Wireless LANs: A theoretical and practical guide. SAMS Publishing, USA (2001)
Xilinx System Generator for DSP v2.2 Reference Guide
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Canet, M.J., Vicedo, F., Almenar, V., Valls, J., de Lima, E.R. (2004). Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_51
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DOI: https://doi.org/10.1007/978-3-540-30117-2_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
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