Abstract
We present in this paper a development method for SOC platforms associating a processor running a RTOS and hardware IP’s. This method is based on encapsulating IP’s for unifying communications and resource sharing between software and hardware tasks. A hardware wrapper that abstracts the IP behaviours through a standard interface and a software encapsulation (the IP Alter Ego) thereby giving access to the Operating System functions are presented. Details about implementing this model on two different FPGA platforms are given.
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Segard, A., Verdier, F. (2004). SOC and RTOS: Managing IPs and Tasks Communications. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_72
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DOI: https://doi.org/10.1007/978-3-540-30117-2_72
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
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