Abstract
We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex. To that end, the FPGA’s reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks. A bus-based communication infrastructure allows for task communication and I/O. We discuss the design of the runtime system and its prototype implementation on an reconfigurable board architecture that was specifically tailored to reconfigurable hardware operating system research.
This work is supported by the Swiss National Science Foundation (SNF) under grant number 2100-59274.99 and by Xilinx, Inc. by hardware donations.
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Walder, H., Platzner, M. (2004). A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_84
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DOI: https://doi.org/10.1007/978-3-540-30117-2_84
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