Abstract
Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.
This work was partially supported by NSF grants CCR-0203813, ACI-0204028, and Hitachi Corporation.
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Bansal, N., Gupta, S., Dutt, N., Nicolau, A., Gupta, R. (2004). Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_95
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DOI: https://doi.org/10.1007/978-3-540-30117-2_95
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