Skip to main content

Error Analysis of Digital Filters Using Theorem Proving

  • Conference paper
Theorem Proving in Higher Order Logics (TPHOLs 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3223))

Included in the following conference series:

Abstract

When a digital filter is realized with floating-point or fixed-point arithmetics, errors and constraints due to finite word length are unavoidable. In this paper, we show how these errors can be mechanically analysed using the HOL theorem prover. We first model the ideal real filter specification and the corresponding floating-point and fixed-point implementations as predicates in higher-order logic. We use valuation functions to find the real values of the floating-point and fixed-point filter outputs and define the error as the difference between these values and the corresponding output of the ideal real specification. Fundamental analysis lemmas have been established to derive expressions for the accumulation of roundoff error in parametric Lth-order digital filters, for each of the three canonical forms of realization: direct, parallel, and cascade. The HOL formalization and proofs are found to be in a good agreement with existing theoretical paper-and-pencil counterparts.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Akbarpour, B., Tahar, S., Dekdouk, A.: Formalization of Cadence SPW Fixed-Point Arithmetic in HOL. In: Butler, M., Petre, L., Sere, K. (eds.) IFM 2002. LNCS, vol. 2335, pp. 185–204. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  2. Akbarpour, B., Tahar, S.: Modeling SystemC Fixed-Point Arithmetic in HOL. In: Dong, J.S., Woodcock, J. (eds.) ICFEM 2003. LNCS, vol. 2885, pp. 206–225. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  3. Cadence Design Systems, Inc., Signal Processing WorkSystem (SPW) User’s Guide, USA (July 1999)

    Google Scholar 

  4. Forsythe, G., Moler, C.B.: Computer Solution of Linear Algebraic Systems. Prentice-Hall, Englewood Cliffs (1967)

    MATH  Google Scholar 

  5. Gordon, M.J.C., Melham, T.F.: Introduction to HOL: A Theorem Proving Environment for Higher-Order Logic. Cambridge University Press, Cambridge (1993)

    MATH  Google Scholar 

  6. Gold, B., Radar, C.M.: Effects of Quantization Noise in Digital Filters. In: Proceedings AFIPS Spring Joint Computer Conference, vol. 28, pp. 213–219 (1966)

    Google Scholar 

  7. Harrison, J.R.: Constructing the Real Numbers in HOL. Formal Methods in System Design 5(1/2), 35–59 (1994)

    Article  MATH  Google Scholar 

  8. Harrison, J.R.: A Machine-Checked Theory of Floating-Point Arithmetic. In: Bertot, Y., Dowek, G., Hirschowitz, A., Paulin, C., Théry, L. (eds.) TPHOLs 1999. LNCS, vol. 1690, pp. 113–130. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  9. Harrison, J.R.: Floating-Point Verification in HOL Light: The Exponential Function. Formal Methods in System Design 16(3), 271–305 (2000)

    Article  Google Scholar 

  10. Harrison, J.R., Théry, L.: A Skeptic’s Approach to Combining Hol andMaple. Journal of Automated Reasoning 21, 279–294 (1998)

    Article  MATH  MathSciNet  Google Scholar 

  11. Huhn, M., Schneider, K., Kropf, T., Logothetis, G.: Verifying Imprecisely Working Arithmetic Circuits. In: Proceedings Design Automation and Test in Europe Conference, March 1999, pp. 65–69 (1999)

    Google Scholar 

  12. Jackson, L.B.: Roundoff-Noise Analysis for Fixed-Point Digital Filters Realized in Cascade or Parallel Form. IEEE Transactions on Audio and Electroacoustics, AU-18, 107–122 (1970)

    Google Scholar 

  13. Kaiser, J.F.: Digital Filters. In: Kuo, F.F., Kaiser, J.F. (eds.) System Analysis by Digital Computer, pp. 218–285. Wiley, Chichester (1966)

    Google Scholar 

  14. Knowles, J.B., Edwards, R.: Effects of a Finite-Word-Length Computer in a Sampled-Data Feedback System. IEE Proceedings 112, 1197–1207 (1965)

    Google Scholar 

  15. Liu, B., Kaneko, T.: Error Analysis of Digital Filters Realized with Floating- Point Arithmetic. Proceedings of the IEEE 57, 1735–1747 (1969)

    Article  Google Scholar 

  16. Mathworks, Inc., Simulink Reference Manual, USA (1996)

    Google Scholar 

  17. Oppenheim, V., Weinstein, C.J.: Effects of Finite Register Length in Digital Filtering and the Fast Fourier Transform. Proceedings of the IEEE 60(8), 957–976 (1972)

    Article  Google Scholar 

  18. Oppenheim, V., Schafer, R.W.: Discrete-Time Signal Processing. Prentice-Hall, Englewood Cliffs (1989)

    MATH  Google Scholar 

  19. Sandberg, W.: Floating-Point-Roundoff Accumulation in Digital Filter Realization. The Bell System Technical Journal 46, 1775–1791 (1967)

    Google Scholar 

  20. Synopsys, Inc., CoCentricTM System Studio User’s Guide, USA (August. 2001)

    Google Scholar 

  21. Weinstein, C., Oppenheim, A.V.: A Comparison of Roundoff Noise in Floating Point and Fixed Point Digital Filter Realizations. Proceedings of the IEEE (Proceedings Letters) 57, 1181–1183 (1969)

    Google Scholar 

  22. Keding, H., Willems, M., Coors, M., Meyr, H.: FRIDGE: A Fixed-Point Design and Simulation Environment. In: Proceedings Design Automation and Test in Europe Conference, February 1998, pp. 429–435 (1998)

    Google Scholar 

  23. Wilkinson, J.H.: Rounding Errors in Algebraic Processes. Prentice-Hall, Englewood Cliffs (1963)

    MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Akbarpour, B., Tahar, S. (2004). Error Analysis of Digital Filters Using Theorem Proving. In: Slind, K., Bunker, A., Gopalakrishnan, G. (eds) Theorem Proving in Higher Order Logics. TPHOLs 2004. Lecture Notes in Computer Science, vol 3223. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30142-4_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-30142-4_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23017-5

  • Online ISBN: 978-3-540-30142-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics