Skip to main content
SpringerLink
Log in

Stubborn Sets for Priority Nets

  • Conference paper
Computer and Information Sciences - ISCIS 2004 (ISCIS 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3280))

Included in the following conference series:

  • 789 Accesses

Abstract

Partial order methods, such as the stubborn set method and the priority method, reduce verification effort by exploiting irrelevant orders of events. We show how the stubborn set method can be applied to priority nets. By applicability we mean that for a given priority net, the stubborn set method constructs a reduced reachability graph that sufficiently represents the full reachability graph of the priority net. This work can also be considered as a combination of the stubborn set method and the priority method, to be used in “complete or moderated incomplete” verification when the original models are unprioritised nets.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Bause, F.: Analysis of Petri Nets with a Dynamic Priority Method. In: Azéma, P., Balbo, G. (eds.) ICATPN 1997. LNCS, vol. 1248, pp. 215–234. Springer, Heidelberg (1997)

    Google Scholar 

  2. Belluomini, W., Myers, C.J.: Efficient Timing Analysis Algorithms for Timed State Space Exploration. In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 88–100. IEEE Computer Society Press, Los Alamitos (1997)

    Chapter  Google Scholar 

  3. Bengtsson, J., Jonsson, B., Lilius, J., Yi, W.: Partial Order Reductions for Timed Systems. In: Sangiorgi, D., de Simone, R. (eds.) CONCUR 1998. LNCS, vol. 1466, pp. 485–500. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  4. Best, E., Koutny, M.: Petri Net Semantics of Priority Systems. Theoretical Computer Science 96(1), 175–215 (1992)

    Article  MATH  MathSciNet  Google Scholar 

  5. Chiola, G., Donatelli, S., Franceschinis, G.: Priorities, Inhibitor Arcs and Concurrency in P/T Nets. In: 12th International Conference on Application and Theory of Petri Nets, Gjern, Denmark, pp. 182–205 (1991)

    Google Scholar 

  6. Dams, D., Gerth, R., Knaack, B., Kuiper, R.: Partial-Order Reduction Techniques for Real-Time Model Checking. Formal Aspects of Computing 10(5-6), 469–482 (1998)

    Article  MATH  Google Scholar 

  7. Flanagan, C., Qadeer, S.: Transactions for Software Model Checking. In: SoftMC 2003: Workshop on Software Model Checking. Electronic Notes in Theoretical Computer Science, vol. 89(3), Elsevier, Amsterdam (2003)

    Google Scholar 

  8. Gerth, R., Kuiper, R., Peled, D., Penczek, W.: A Partial Order Approach to Branching Time Logic Model Checking. In: 3rd Israel Symposium on the Theory of Computing and Systems, pp. 130–139. IEEE Computer Society Press, Los Alamitos (1995)

    Chapter  Google Scholar 

  9. Godefroid, P.: Using Partial Orders to Improve Automatic Verification Methods. In: Clarke, E., Kurshan, R.P. (eds.) CAV 1990. LNCS, vol. 531, pp. 176–185. Springer, Heidelberg (1991)

    Chapter  Google Scholar 

  10. Godefroid, P.: Model Checking for Programming Languages Using VeriSoft. In: 24th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp. 174–186. ACM Press, New York (1997)

    Chapter  Google Scholar 

  11. Godefroid, P., Wolper, P.: A Partial Approach to Model Checking. In: 6th Annual IEEE Symposium on Logic in Computer Science, pp. 406–415. IEEE Computer Society Press, Los Alamitos (1991)

    Chapter  Google Scholar 

  12. Groote, J.F., Sellink, M.P.A.: Confluence for Process Verification. In: Lee, I., Smolka, S.A. (eds.) CONCUR 1995. LNCS, vol. 962, pp. 204–218. Springer, Heidelberg (1995)

    Google Scholar 

  13. Hack, M.: Petri Net Languages. Computation Structures Group Memo 124, Project MAC, Massachusetts Institute of Technology, Cambridge, MA, USA (1975)

    Google Scholar 

  14. Helsinki University of Technology: PROD (Reachability Analysis Tool). Espoo, Finland, http://www.tcs.hut.fi/Software/prod/

  15. Holzmann, G.J., Peled, D.: An Improvement in Formal Verification. In: Formal Description Techniques VII (FORTE 1994), pp. 197–211. Chapman & Hall, Boca Raton (1995)

    Google Scholar 

  16. Itoh, M., Ichikawa, H.: Protocol Verification Algorithm Using Reduced Reachability Analysis. The Transactions of the IECE of Japan 66(2), 88–93 (1983)

    Google Scholar 

  17. Janicki, R., Koutny, M.: Using Optimal Simulations to Reduce Reachability Graphs. In: Clarke, E., Kurshan, R.P. (eds.) CAV 1990. LNCS, vol. 531, pp. 166–175. Springer, Heidelberg (1991)

    Chapter  Google Scholar 

  18. Kurshan, R., Levin, V., Minea, M., Peled, D., Yenigün, H.: Verifying Hardware in Its Software Context. In: 1997 IEEE/ACM International Conference on Computer- Aided Design, pp. 742–749. IEEE Computer Society Press, Los Alamitos (1997)

    Google Scholar 

  19. Liu, H., Miller, R.E.: Generalized Fair Reachability Analysis for Cyclic Protocols: Part 1. In: Protocol Specification, Testing and Verification XIV (PSTV 1994), pp. 271–286. Chapman & Hall, Boca Raton (1995)

    Google Scholar 

  20. Mercer, E.G., Myers, C.J., Yoneda, T., Zheng, H.: Modular Synthesis of Timed Circuits using Partial Orders on LPNs. In: Theory and Practice of Timed Systems. Electronic Notes in Theoretical Computer Science, vol. 65(6), Elsevier, Amsterdam (2002)

    Google Scholar 

  21. Minea, M.: Partial Order Reduction for Verification of Timed Systems. Doctoral Dissertation, Report CMU-CS-00-102, School of Computer Science, Carnegie Mellon University, Pittsburgh, PA, USA (1999)

    Google Scholar 

  22. Özdemir, K., Ural, H.: Deadlock Detection in CFSM Models via Simultaneously Executable Sets. In: 6th International Conference on Communication and Information, Peterborough, Ontario, Canada, pp. 673–688 (1994)

    Google Scholar 

  23. Pagani, F.: Partial Orders and Verification of Real-Time Systems. In: Jonsson, B., Parrow, J. (eds.) FTRTFT 1996. LNCS, vol. 1135, pp. 327–346. Springer, Heidelberg (1996)

    Google Scholar 

  24. Peled, D.: All from One, One for All: on Model Checking Using Representatives. In: Courcoubetis, C. (ed.) CAV 1993. LNCS, vol. 697, pp. 409–423. Springer, Heidelberg (1993)

    Google Scholar 

  25. Quemada, J.: Compressed State Space Representation in LOTOS with the Interleaved Expansion. In: Protocol Specification, Testing and Verification XI (PSTV 1991), pp. 19–35. North-Holland, Amsterdam (1991)

    Google Scholar 

  26. Roch, S.: Stubborn Sets of Signal-Event Nets. In: Workshop on Concurrency, Specification and Programming, Informatik-Bericht 110, Institut für Informatik, Humboldt-Universität zu Berlin, Germany, pp. 197–203 (1998)

    Google Scholar 

  27. Schmidt, K.: Stubborn Sets for Model Checking the EF/AG Fragment of CTL. Fundamenta Informaticae 43(1-4), 331–341 (2000)

    MATH  MathSciNet  Google Scholar 

  28. Sęn, M.A.: Verification of SDL Systems with Partial Order Methods. Master’s Thesis, Department of Electrical and Electronics Engineering, Middle East Technical University, Ankara, Turkey (1997)

    Google Scholar 

  29. Sloan, R.H., Buy, U.: Stubborn Sets for Real-Time Petri Nets. Formal Methods in System Design 11(1), 23–40 (1997)

    Article  Google Scholar 

  30. Stoller, S.D.: Model-Checking Multi-threaded Distributed Java Programs. In: Havelund, K., Penix, J., Visser, W. (eds.) SPIN 2000. LNCS, vol. 1885, pp. 224–244. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  31. Teruel, E., Franceschinis, G., De Pierro, M.: Well-Defined Generalized Stochastic Petri Nets: A Net-Level Method to Specify Priorities. IEEE Transactions on Software Engineering 29(11), 962–973 (2003)

    Article  Google Scholar 

  32. Toggweiler, D., Grabowski, J., Hogrefe, D.: Partial Order Simulation of SDL Specifications. In: SDL 1995: With MSC in CASE, pp. 293–306. North-Holland, Amsterdam (1995)

    Google Scholar 

  33. Valmari, A.: Error Detection by Reduced Reachability Graph Generation. In: 9th European Workshop on Application and Theory of Petri Nets, Venice, Italy, pp. 95–112 (1988)

    Google Scholar 

  34. Valmari, A.: Heuristics for Lazy State Space Generation Speeds up Analysis of Concurrent Systems. In: STeP 1988, Finnish Artificial Intelligence Symposium, Helsinki, Finland, pp. 640–650 (1998)

    Google Scholar 

  35. Valmari, A.: A Stubborn Attack on State Explosion. In: Clarke, E., Kurshan, R.P. (eds.) CAV 1990. LNCS, vol. 531, pp. 156–165. Springer, Heidelberg (1991)

    Chapter  Google Scholar 

  36. Valmari, A.: Stubborn Sets of Coloured Petri Nets. In: 12th International Conference on Application and Theory of Petri Nets, Gjern, Denmark, pp. 102–121 (1991)

    Google Scholar 

  37. Valmari, A., Clegg, M.: Reduced Labelled Transition Systems Save Verification Effort. In: Groote, J.F., Baeten, J.C.M. (eds.) CONCUR 1991. LNCS, vol. 527, pp. 526–540. Springer, Heidelberg (1991)

    Google Scholar 

  38. Valmari, A., Tiusanen, M.: A Graph Model for Efficient Reachability Analysis of Description Languages. In: 8th European Workshop on Application and Theory of Petri Nets, Zaragoza, Spain, pp. 349–366 (1987)

    Google Scholar 

  39. Varpaaniemi, K.: On the Stubborn Set Method in Reduced State Space Generation. Doctoral Dissertation, Report A 51, Digital Systems Laboratory, Helsinki University of Technology, Espoo, Finland (1998)

    Google Scholar 

  40. Yoneda, T., Nakade, K., Tohma, Y.: A Fast Timing Verification Method Based on The Independence of Units. In: 19th International Symposium on Fault-Tolerant Computing, pp. 134–141. IEEE Computer Society Press, Los Alamitos (1989)

    Google Scholar 

  41. Yoneda, T., Shibayama, A., Schlingloff, B.H., Clarke, E.M.: Efficient Verification of Parallel Real-Time Systems. In: Courcoubetis, C. (ed.) CAV 1993. LNCS, vol. 697, pp. 321–332. Springer, Heidelberg (1993)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Laboratory for Theoretical Computer Science, Helsinki University of Technology, P.O. Box 5400, FIN-02015 HUT, Espoo, Finland

    Kimmo Varpaaniemi

Authors
  1. Kimmo Varpaaniemi
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Engineering, Bilkent University, TR-06800, Bilkent, Ankara, Turkey

    Cevdet Aykanat

  2. No Affiliation,  

    Tuǧrul Dayar

  3. Department of Computer Engineering, Bilkent University, 06800, Bilkent, Ankara, Turkey

    İbrahim Körpeoğlu

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Varpaaniemi, K. (2004). Stubborn Sets for Priority Nets. In: Aykanat, C., Dayar, T., Körpeoğlu, İ. (eds) Computer and Information Sciences - ISCIS 2004. ISCIS 2004. Lecture Notes in Computer Science, vol 3280. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30182-0_58

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-30182-0_58

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23526-2

  • Online ISBN: 978-3-540-30182-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation