Connecting E-Dreams to Deep-Submicron Realities

Abstract

Today’s electronics industry is making the transition from a PC centric world towards Weiser’s world of pervasive computing and communication. Mass produced intelligent micro-systems will be present in virtually every person and every object he/she is in touch with. System sce-narists create a plethora of e-Dreams whereby the world starts to adapt to the wishes of the consumer wherever he/she may be.

The adaptiveness of such systems means that these global distributed systems must autono-mously organise themselves and adapt to new services without much user interaction. There-fore such systems are software intensive by nature and run on extremely complex and nomadic silicon platforms. In addition, they require human centric interfaces to augment our senses, control our health, wellness, comfort, security and mobility. Most are wearable or permanently hidden in the infrastructure and hence must be low- to ultra-low energy devices.

On the other hand, the technology push for these e-Dreams comes from the relentless CMOS scaling that will reach the 30nm scale in the next decade. Then device sizes start to match the size of bio-and other molecules. Mems are evolving into self-assembled Nems, CMOS will become compatible with all sorts of new materials and multiple dies will be pack-aged to extremely intelligent e-grains possible scavenging their energy from the environment.

Hence, we are witnessing two worlds that, on the one end, enable themselves but, on the other hand, we see the conceptual gap between these two worlds increase at a Moore type rate.

This talk will focus on a number of challenges resulting from the growing distance between “atoms” and “ities”. Atoms refer to the nano-scale physics of the underlying devices while “Ities” refers to the expectations of the e-Dreams such as: reliability, dependability, security, adaptivity, interoperability, manufacturability etc.

More in particular the following aspects will be discussed:

• 1 How to cope with the energy-flexibility-cost issue given the computational power required for nomadic and consumer devices as well as smart sensors for personal wellness and infra-structure monitoring and control. Particular attention must be paid to novel compute and communication architectures, low power memory architectures but also to the creation of the software layers to map e-Dreams on these architectures to operate at lowest possible en-ergy and with guaranteed quality of service in spite of the physical uncertainties caused by nano-scale physics. This provides an enormous challenge to master design complexity far above what today’s EDA industry is delivering or that software engineering can produce in a reliable way.

• 2 Nano-scale physics will profoundly jeopardize the digital abstraction paradigm that allowed us to design very complex digital systems. When scaling below 90nm we have to design systems of 1 billion transistors while, at the same time, coping with increasing gate- and subthreshold leakage power, uncertainty due to the stochastic and discrete nature of doping and lithography and delay dominance by interconnect. Hence designing for worst-case con-ditions is no longer an option if we want to exploit further scaling. Doing better will require novel design flows based on optimal mapping of applications based on run-time monitoring of timing-power trade-off of the architectural components on-chip. We will present some possible solutions based on multiple Pareto-optimal mappings at design time combined with a run-time optimal control algorithm based on run-time monitoring of timing-power and temperature of chip components.