Abstract
Deep sub-micron effects influence the signal transmission especially on global wires. In order to select communication architectures, minimize power dissipation and improve signal integrity it is necessary to explore DSM effects already at high levels of design abstraction. Therefore in this paper we present a parameterized high-level simulation model which is based on SPICE simulations and evaluates therefore signal integrity and power dissipation very accurately. The maximum error of our model was 1.3%. In comparism to a full SPICE simulation the required computation time could be reduced by a factor of up to 900.
This work is funded by the German Science Foundation DFG within the joint project VIVA under MU 1024/5-3.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Sylvester, D., Keutzer, K.: Getting to the Bottom of Deep Submicron. In: ICCAD (1998)
Sakurai, T.: Design challenges for 0.1 μm and beyond. In: ASP-DAC (2000)
Sylvester, D., Keutzer, K.: Impact of Small Process Geometries on Microarchitectures in Systems on a Chip. Proceedings of the IEEE 89(4), 467–489 (2001)
Kuhlmann, M., Sapatnekar, S.S.: Exact and efficient crosstalk estimation. IEEE Transactions on Computer-Aided Design 20(7), 858–866 (2001)
Uchino, T., Cong, J.: An interconnect energy model considering coupling effects. IEEE Transactions on Computer-Aided Design 21(7), 763–776 (2002)
Kapur, P., Chandra, G., Saraswat, K.C.: Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. In: Design Automation Conference, June 2002, pp. 461–466 (2002)
Sylvester, D., Hu, C.: Analytical modeling and characterization of deep-submicrometer interconnect. Proc. IEEE 89(5), 634–664 (2001)
Macii, E., Pedram, M., Somenzi, F.: High-level power modeling, estimation, and optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(11), 1061–1079 (1998)
Heydari, P., Pedram, M.: Interconnect energy dissipation modeling in high-speed ULSI circuits. In: ASP DAC, January 2002, pp. 132–140 (2002)
Sotiriadis, P., Chandrakasan, A.: A bus energy model for deep sub-micron technology. IEEE Transacitons on VLSI (2002)
Taylor, C., Dey, S.: andY. Zhao. Modeling and minimization of interconnect energy dissipation in nanometer technologies. In: DAC (2001)
Gupta, P., Zhong, L., Jha, N.K.: A high-level interconnect power model for design space exploration. In: ICCAD (2003)
Bai, X., Dey, S.: High-level crosstalk defect simulation for system-on-chip interconnects. In: IEEE VLSI Test Symposium, March 2001, pp. 169–175 (2001)
Stan, M.R., Burleson, W.P.: Bus-Invert Coding for Low-Power I/O. Transactions on VLSI Systems 3, 49–58 (1995)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kretzschmar, C., Bitterlich, T., Müller, D. (2004). A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_11
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive