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An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3254))

Abstract

Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maximum vertex degree as the constraint. Given a collection of n points in the plane, we firstly construct a graph named the bounded-degree neighborhood graph (BNG). Based on this framework, we propose an O(n log n) algorithm to construct a 4-BDRMST (RMST with maximum vertex degree ( 4). This is the first 4-BDRMST algorithm with such a complexity, and experimental results show that the algorithm is significantly faster than the existing 4-BDRMST algorithms.

This work was supported in part by the NSFC under Grant No.60373012 and No. 60121120706, the SRFDP of China under Grant No.20020003008, and the Hi-Tech Research and Development (863) Program of China under Grant No.2002AA1Z1460.

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Authors and Affiliations

  1. Dept. of Computer Science and Technology, Tsinghua Univ, Beijing, 100084, P. R. China

    Yin Wang, Xianlong Hong, Tong Jing & Yang Yang

  2. Institution of Applied Mathematics, Chinese Academy of Sciences, Beijing, 100080, P. R. China

    Xiaodong Hu & Guiying Yan

Authors
  1. Yin Wang
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  2. Xianlong Hong
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  3. Tong Jing
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  4. Yang Yang
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  5. Xiaodong Hu
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  6. Guiying Yan
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Editor information

Editors and Affiliations

  1. Politecnico di Torino, 10129, Torino, Italy

    Enrico Macii

  2. Electrical and Computer Engineering Department, University of Patras, Greece

    Vassilis Paliouras

  3. Department of Electrical and Computer Engineering, University of Patras, Patras, Greece

    Odysseas Koufopavlou

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© 2004 Springer-Verlag Berlin Heidelberg

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Wang, Y., Hong, X., Jing, T., Yang, Y., Hu, X., Yan, G. (2004). An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_46

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  • DOI: https://doi.org/10.1007/978-3-540-30205-6_46

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23095-3

  • Online ISBN: 978-3-540-30205-6

  • eBook Packages: Springer Book Archive

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