Abstract
Many techniques are used to control the speed of digital designs at architecture level [1] or to stop the clock at gate level, mainly to save power [2]. Some high speed circuits speed up the clock on portions of the design which were not critical otherwise [3]. Asynchronous designs are fine grain speed adaptive, but this solution is not easy to use [4].This article presents an efficient and easy to use technique to increase performance of synthesized digital circuits with low level adaptive speed – i.e. at gate level.
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© 2004 Springer-Verlag Berlin Heidelberg
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Valencia, L. (2004). Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_70
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DOI: https://doi.org/10.1007/978-3-540-30205-6_70
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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