Abstract
In this paper, we describe a generic timing mechanism, which allows building mixed-level simulation environments that facilitate timing closure for their gate-level modules whilst simulating a whole System-on-Chip (SoC) made of modules at different levels of abstraction. The APPLES gate level accelerator provides fast timing-accurate simulation of gate-level designs. But to enable its use for large SoC-designs, a generic timing mechanism must be developed in order to use the APPLES processor in a mixed-level environment together with higher-level simulation engines. The environment we present here makes use of a universal time mechanism and a flexible client-server implementation to enable a generic and expandable system for mixed-level, mixed-language timing simulation.
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© 2004 Springer-Verlag Berlin Heidelberg
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Maili, A., Dalton, D., Steger, C. (2004). A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_82
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DOI: https://doi.org/10.1007/978-3-540-30205-6_82
Publisher Name: Springer, Berlin, Heidelberg
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