Abstract
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this regard, but bounded model checking (BMC) shows some promise. However, unlike traditional model checking, for which time systems have been thoroughly researched, BMC is less capable of modeling timing behavior – an essential task for verifying many types of software. Here we describe a new bounded model checker we have named xBMC, which we believe solves the reachability problem of dense-time systems. In xBMC, regions and transition relations are represented as Boolean formulae using discrete interpretations. In an experiment using well- developed model checkers to verify Fischer’s protocol, xBMC outperformed both traditional (Kronos [8], Uppaal [16], and Red [26]) and bounded (SAL [21]) model checkers by being able to verify up to 22 processes, followed by Red with 15 processes. Therefore, although xBMC is less efficient in guaranteeing system correctness, it provides an effective and practical method for timing behavior verification of large systems.
This work is partially supported by National Science Council NSC 92-2213-E-001 -023-.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Alur, R., Courcoubetis, C., Dill, D.: Model-checking for Real-time Systems. In: IEEE 5th Annual Symposium on Logi In Computer Science (LICS), Philadelphia (June 1990)
Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science 126, 183–235 (1994)
Amla, N., Kurshan, R., McMillan, K., Medel, R.K.: Experimental Analysis of Different Techniques for Bounded Model Checking. In: Garavel, H., Hatcliff, J. (eds.) TACAS 2003. LNCS, vol. 2619, pp. 34–48. Springer, Heidelberg (2003)
Asarin, E., Bozga, M., Kerbrat, A., Maler, O., Pnueli, A., Rasse, A.: Data-structures for the Verification of Timed Automata. In: Maler, O. (ed.) HART 1997. LNCS, vol. 1201, pp. 346–360. Springer, Heidelberg (1997)
Audemard, G., Cimatti, A., Korniowicz, A., Sebastiani, R.: Bounded Model Checking for Timed Systems. In: Peled, D.A., Vardi, M.Y. (eds.) FORTE 2002. LNCS, vol. 2529, pp. 243–259. Springer, Heidelberg (2002)
Beer, I., Ben-David, S., Landver, A.: On-the Fly Model Checking of RCTL Formulas. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, Springer, Heidelberg (1994)
Biere, A., Cimatti, A., Clarke, E.M., Fujita, M., Zhu, Y.: Symbolic Model Checking Using SAT Procedures Instead of BDDs. In: Proc. DAC 1999, pp. 317–320 (1999)
Bozga, M., Daws, C., Maler, O., Olivero, A., Tripakis, S., Yovine, S.: Kronos: a Model-Checking Tool for Real-Time Systems. In: Y. Vardi, M. (ed.) CAV 1998. LNCS, vol. 1427, Springer, Heidelberg (1998)
Clarke, E., Biere, A., Raimi, R., Zhu, Y.: Bounded Model Checking Using Satisfiability Solving. In: Formal Methods in System Design (July 2001)
Clarke, E., Kroening, D., Yorav, K.: Behavioral Consistency of C and Verilog Programs using Bounded Model Checking. In: Proc. DAC 2003, Session 23.3, Anaheim, CA (2003)
Göllü, A., Puri, A., Varaiya, P.: Discretization of timed automata. In: Proc. of the 33rd IEEE conferene on decision and control, pp. 957–958 (1994)
Henzinger, T.A., Nicollin, X., Sifakis, J., Yovine, S.: Symbolic Model Checking for Real-Time Systems. Information and Computation 111, 193–244 (1994)
Huang, Y.-W., Yu, F., Hang, C., Tsai, C.-H., Lee, D.-T., Kuo, S.-Y.: Verifying Web Applications Using Bounded Model Checking. In: Proc. DSN 2004, Italy (June 2004)
Laroussinie, F., Larsen, K.G., Weise, C.: From timed automata to logic - and back. In: Hájek, P., Wiedermann, J. (eds.) MFCS 1995. LNCS, vol. 969, pp. 529–539. Springer, Heidelberg (1995)
Larsen, K.G., Pettersson, P., Wang, Y.: Compositional and Symbolic Model Checking of Real-time System. In: Proc. RTSS 1995, Pisa, Italy (1995)
Larsen, K.G., Pettersson, P., Wang, Y.: UPPAAL in a Nutshell. Int. Journal on Software Tools for Technology Transfer 1(1-2), 134–152 (1998)
Lu, F., Wnag, L.-C., Cheng, K.-T., Huan, R.C.-Y.: A Circuit SAT Solver With Signal Correlation Guided Learning. In: Proc. DATE 2003 (March 2003)
Moller, M.O., Rue, H., Sorea, M.: Predicate Abstraction for Dense Real-time Systems. In: Theory and Practice of Timed Systems, TPTS 2002 (2002)
Moskewicz, M.W., Madigan, C.F., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an Efficient SAT Solver. In: Proc. DAC (June 2001)
de Moura, L., Rueß, H., Sorea, M.: Lazy Theorem Proving for Bounded Model Checking over Infinite Domains. In: Voronkov, A. (ed.) CADE 2002. LNCS (LNAI), vol. 2392, pp. 438–455. Springer, Heidelberg (2002)
de Moura, L., Owre, S., Rueß, H., Rushby, J., Shanker, N., Sorea, M.: SAL 2. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 496–500. Springer, Heidelberg (2004)
Niebert, P., Mahfoudh, M., Asarin, E., Bozga, M., Jain, N., Maler, O.: Verification of Timed Automata via Satisfiability Checking. In: Damm, W., Olderog, E.-R. (eds.) FTRTFT 2002. LNCS, vol. 2469, p. 225. Springer, Heidelberg (2002)
Penczek, W., Wozna, B., Zbrzezny, A.: Towards Bounded Model Checking for the Universal Fragment of TCTL. In: Damm, W., Olderog, E.-R. (eds.) FTRTFT 2002. LNCS, vol. 2469, pp. 265–288. Springer, Heidelberg (2002)
Seshia, S.A., Bryant, R.E.: Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 154–166. Springer, Heidelberg (2003)
Sorea, M.: Bounded Model Checking for Timed Automata. CSL Technical Report SRICSL- 02-03 (2002)
Wang, F.: Efficient Verification of Timed Automata with BDD-like Data-Structures. In: Zuck, L.D., Attie, P.C., Cortesi, A., Mukhopadhyay, S. (eds.) VMCAI 2003. LNCS, vol. 2575, pp. 189–205. Springer, Heidelberg (2002)
Wozna, B., Penczek, W., Zbrzezny, A.: Checking Reachability Properties for Timed Automata via SAT. Fundamenta Informaticae 55(2), 223–241 (2003)
Yovine, S.: Model-checking Timed Automata. In: Rozenberg, G. (ed.) EEF School 1996. LNCS, vol. 1494, Springer, Heidelberg (1998)
Yu, F., Wang, B.-Y.: Toward Unbounded Model Checking for Region Automata (paper submitted)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yu, F., Wang, BY., Huang, YW. (2004). Bounded Model Checking for Region Automata. In: Lakhnech, Y., Yovine, S. (eds) Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems. FTRTFT FORMATS 2004 2004. Lecture Notes in Computer Science, vol 3253. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30206-3_18
Download citation
DOI: https://doi.org/10.1007/978-3-540-30206-3_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23167-7
Online ISBN: 978-3-540-30206-3
eBook Packages: Springer Book Archive