Abstract
An automatic traffic sign detection system would be important in a driver assistance system. In this paper, an approach for detecting numbers on speed limit signs is proposed. Such a system would have to provide a high recognition performance in real-time. Thus, in this paper we propose to apply evolvable hardware for the classification of the numbers extracted from images. The system is based on incremental evolution of digital logic gates. Experiments show that this is a very efficient approach.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Goldberg, D.: Genetic Algorithms in search, optimization, and machine learning. Addision–Wesley, Reading (1989)
Lee, W.-P., Hallam, J., Lund, H.H.: Learning complex robot behaviours by evolutionary computing with task decomposition. In: Birk, A., Demiris, J. (eds.) EWLR 1997. LNCS (LNAI), vol. 1545, pp. 155–172. Springer, Heidelberg (1998)
Sekanina, L., Torresen, J.: Detection of Norwegian speed limit signs. In: Proc. of the 16th European Simulation Multiconference (ESM 2002), SCS Europe, June 2002, pp. 337–340 (2002)
Thomas, R.: Less is more [intelligent speed adaptation for road vehicles]. IEE Review 49(5), 40–43 (2003)
Torresen, J.: A divide-and-conquer approach to evolvable hardware. In: Sipper, M., Mange, D., Pérez-Uribe, A. (eds.) ICES 1998. LNCS, vol. 1478, pp. 57–65. Springer, Heidelberg (1998)
Torresen, J.: Scalable evolvable hardware applied to road image recognition. In: Lohn, J., et al. (eds.) Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, July 2000, pp. 245–252. IEEE Computer Society, Silicon Valley (2000)
Torresen, J.: Two-step incremental evolution of a digital logic gate based prosthetic hand controller. In: Liu, Y., Tanaka, K., Iwata, M., Higuchi, T., Yasunaga, M. (eds.) ICES 2001. LNCS, vol. 2210, pp. 1–13. Springer, Heidelberg (2001)
Torresen, J.: A scalable approach to evolvable hardware. Journal of Genetic Programming and Evolvable Machines 3(3), 259–282 (2002)
Yao, X., Higuchi, T.: Promises and challenges of evolvable hardware. In: Higuchi, T., Iwata, M., Weixin, L. (eds.) ICES 1996. LNCS, vol. 1259, pp. 55–78. Springer, Heidelberg (1997)
Yasunaga, M., et al.: Genetic algorithm-based design methodology for pattern recognition hardware. In: Miller, J.F., Thompson, A., Thompson, P., Fogarty, T.C. (eds.) ICES 2000. LNCS, vol. 1801, pp. 264–273. Springer, Heidelberg (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Torresen, J., Bakke, J.W., Sekanina, L. (2004). Recognizing Speed Limit Sign Numbers by Evolvable Hardware. In: Yao, X., et al. Parallel Problem Solving from Nature - PPSN VIII. PPSN 2004. Lecture Notes in Computer Science, vol 3242. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30217-9_69
Download citation
DOI: https://doi.org/10.1007/978-3-540-30217-9_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23092-2
Online ISBN: 978-3-540-30217-9
eBook Packages: Springer Book Archive